Nios II Classic Software Developer’s Handbook

ID 683282
Date 5/14/2015
Public
Document Table of Contents

9.4.1. HAL Behavior for Nios II Device Driver Cache Considerations

The HAL provides the C-language macros IORD and IOWR that expand to the appropriate assembly instructions to bypass the data cache. The IORD macro expands to the ldwio instruction, and the IOWR macro expands to the stwio instruction. These macros are provided to enable HAL device drivers to access device registers.

All of these macros bypass the data cache when they perform their operation. In general, your program passes values defined in system.h as the BASE and REGNUM parameters. These macros are defined in the file <Nios II EDS install path>/components/altera_nios2/HAL/inc/io.h.

Table 45.  HAL I/O Macros to Bypass the Data Cache
Macro Use
IORD(BASE, REGNUM) Read the value of the register at offset REGNUM in a device with base address BASE. Registers are assumed to be offset by the address width of the bus.
IOWR(BASE, REGNUM, DATA) Write the value DATA to the register at offset REGNUM in a device with base address BASE. Registers are assumed to be offset by the address width of the bus.
IORD_32DIRECT(BASE, OFFSET) Make a 32-bit read access at the location with address BASE+OFFSET.
IORD_16DIRECT(BASE, OFFSET) Make a 16-bit read access at the location with address BASE+OFFSET.
IORD_8DIRECT(BASE, OFFSET) Make an 8-bit read access at the location with address BASE+OFFSET.
IOWR_32DIRECT(BASE, OFFSET, DATA) Make a 32-bit write access to write the value DATA at the location with address BASE+OFFSET.
IOWR_16DIRECT(BASE, OFFSET, DATA) Make a 16-bit write access to write the value DATA at the location with address BASE+OFFSET.
IOWR_8DIRECT(BASE, OFFSET, DATA) Make an 8-bit write access to write the value DATA at the location with address BASE+OFFSET.