F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 10/04/2021
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2.4. Interface Signals

Table 5.  Design Example Interface Signals
Signal Direction Description
ref_clk100MHz Input Input clock for CSR access on all the reconfiguration interfaces. Drive at 100 MHz.
i_clk_ref[0] Input Reference clock for System PLL. Drive at 156.25 MHz.
i_clk_ref[1] Input Transceiver reference clock. Drive at
  • 153.6 MHz for CPRI line rate 1.2, 2.4, 3, 4.9, 6.1, and 9.8 Gbps.
  • 184.32 MHz for CPRI line rates 10.1,12.1, and 24.3 Gbps with and without RS-FEC.
i_rx_serial[n] Input Transceiver PHY input serial data.
o_tx_serial[n] Output Transceiver PHY output serial data.
Level Two Title