F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 10/04/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Features 2.2. Simulation Design Example 2.3. Hardware Design Example 2.4. Interface Signals 2.5. Design Example Registers
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.10.04 21.3 3.0.0
  • Added support for new simulators in section: Hardware and Software Requirements.
  • Updated steps in section: Simulating the Design Example Testbench.
  • Updated the following sections with new line rate information:
    • Design Example Description
    • Simulation Design Example
    • Interface Signals
  • Updated the address in section: Design Example Registers.
2021.06.21 21.2 2.0.0 Initial release.
Level Two Title