2.3. Hardware Design Example
Figure 5. Hardware Design Example Block Diagram
The F-Tile CPRI PHY Intel® FPGA IP core hardware design example includes the following components:
- F-Tile CPRI PHY Intel® FPGA IP core.
- Packet client logic block that generates and receives traffic.
- Round trip counter.
- IOPLL to generate sampling clock for deterministic latency logic inside the IP, and round trip counter component at testbench.
- System PLL to generate system clocks for the IP.
- Avalon® -MM address decoder to decode reconfiguration address space for CPRI, Transceiver, and Ethernet modules during reconfiguration accesses.
- Sources and probes for asserting resets and monitoring the clocks and a few status bits.
- JTAG controller that communicates with the System Console. You communicate with the client logic through System Console.