F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

Download PDF
ID 683281
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Features 2.2. Simulation Design Example 2.3. Hardware Design Example 2.4. Interface Signals 2.5. Design Example Registers
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

1.4. Simulating the Design Example Testbench

Procedure

Follow these steps to simulate the testbench:

  1. At the command prompt, change to the testbench simulation directory <design_example_dir>/example_testbench. 
    cd <my_design>/example_testbench
  2. Run quartus_tlg on the generated project file: 
    quartus_tlg cpriphy_ftile_hw
  3. Run ip-setup-simulation: 
    ip-setup-simulation --output-directory=./sim_script --use-relative-paths --quartus-project=cpriphy_ftile_hw.qpf
  4. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
  5. Analyze the results. The successful testbench received five hyperframes, and displays "PASSED".
    Table 3.  Steps to Simulate the Testbench in Synopsys VCS* Simulator
    Simulator Instructions
    VCS* In the command line, type:
    sh run_vcs.sh
    VCS* MX In the command line, type:
    sh run_vcsmx.sh
    ModelSim* SE or Questa* or Questa*-Intel® FPGA Edition In the command line, type:
    vsim -do run_vsim.do
    If you prefer to simulate without bringing up the GUI, type: 
    vsim -c -do run_vsim.do
    The following sample output illustrates a successful simulation test run for 24.33024 Gbps with 4 CPRI channels: 
    Ref clock is 184.32 MHz
Waiting for TX ready
TX is ready is high at time              75250000
Waiting for RX ready
RX is ready is high at time             120750000
*** configure DL ***
** Address offset = 0x185d, ReadData  = 0x00000a86
** Address offset = 0x3c00a, ReadData  = 0x000c0000
** Address offset = 0x3c00a, WriteData = 0x000c0a86
** Address offset = 0x3c00a, ReadData  = 0x000c0a86
** Address offset = 0x2, WriteData = 0xc0000000
** Address offset = 0x2, WriteData = 0x00000000
** Address offset = 0x185d, ReadData  = 0x000034a6
** Address offset = 0x3c008, ReadData  = 0x000c0000
** Address offset = 0x3c008, WriteData = 0x000c34a6
** Address offset = 0x3c008, ReadData  = 0x000c34a6
** Address offset = 0x2, WriteData = 0xc0000000
** Address offset = 0x2, WriteData = 0x00000000
** Address offset = 0x185d, ReadData  = 0x00003526
** Address offset = 0x3c006, ReadData  = 0x014c0000
** Address offset = 0x3c006, WriteData = 0x014c3526
** Address offset = 0x3c006, ReadData  = 0x014c3526
** Address offset = 0x2, WriteData = 0xc0000000
** Address offset = 0x2, WriteData = 0x00000000
** Address offset = 0x185d, ReadData  = 0x00001be6
** Address offset = 0x3c004, ReadData  = 0x014c0000
** Address offset = 0x3c004, WriteData = 0x014c1be6
** Address offset = 0x3c004, ReadData  = 0x014c1be6
** Address offset = 0x2, WriteData = 0xc0000000
** Address offset = 0x2, WriteData = 0x00000000
*** sending packets in progress, waiting for checker pass ***
*** waiting for measure_valid to assert...
** Address offset = 0x2, ReadData  = 0x00000003
** measure_valid is asserted.
** Address offset = 0x3, ReadData  = 0x00001ba0
** Address offset = 0x4, ReadData  = 0x000082bf
*** waiting for hyperframe sync to assert...
** hyperframe sync is asserted.
*** waiting for round trip measure...
-> 385120ns: Channel 0: Round trip measure done with count 5151
** Channel 0: RX checker has received packets correctly!
** PASSED
*** waiting for measure_valid to assert...
** Address offset = 0x2, ReadData  = 0x00000003
** measure_valid is asserted.
** Address offset = 0x3, ReadData  = 0x00001b44
** Address offset = 0x4, ReadData  = 0x00008516
*** waiting for hyperframe sync to assert...
** hyperframe sync is asserted.
*** waiting for round trip measure...
-> 385255ns: Channel 1: Round trip measure done with count 5216
** Channel 1: RX checker has received packets correctly!
** PASSED
*** waiting for measure_valid to assert...
** Address offset = 0x2, ReadData  = 0x00000003
** measure_valid is asserted.
** Address offset = 0x3, ReadData  = 0x00001b02
** Address offset = 0x4, ReadData  = 0x0000860c
*** waiting for hyperframe sync to assert...
** hyperframe sync is asserted.
*** waiting for round trip measure...
-> 385385ns: Channel 2: Round trip measure done with count 5240
** Channel 2: RX checker has received packets correctly!
** PASSED
*** waiting for measure_valid to assert...
** Address offset = 0x2, ReadData  = 0x00000003
** measure_valid is asserted.
** Address offset = 0x3, ReadData  = 0x00001a79
** Address offset = 0x4, ReadData  = 0x000083d7
*** waiting for hyperframe sync to assert...
** hyperframe sync is asserted.
*** waiting for round trip measure...
-> 387084ns: Channel 3: Round trip measure done with count 5152
** Channel 3: RX checker has received packets correctly!
** PASSED
**
*****************************************
$finish called from file "basic_avl_tb_top.sv", line 352.
$finish at simulation time 387104ns
Level Two Title