1.3. Directory Structure

F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281

Date 10/04/2021

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Public

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The F-Tile CPRI PHY Intel® FPGA IP core design example file directories contain the following generated files for the design example.

Figure 2. Directory Structure of the Generated Example Design

Table 1. Testbench File Descriptions
File Names	Description
Key Testbench and Simulation Files
<design_example_dir>/example_testbench/basic_avl_tb_top.sv	Top-level testbench file. The testbench instantiates the DUT wrapper and runs Verilog HDL tasks to generate and accept packets.
<design_example_dir>/example_testbench/cpriphy_ftile_wrapper.sv	DUT wrapper that instantiates DUT and other testbench components.
Testbench Scripts¹
<design_example_dir>/example_testbench/run_vsim.do	The Siemens* EDA ModelSim* SE or Questa* or Questa*-Intel® FPGA Edition script to run the testbench.
<design_example_dir>/example_testbench/run_vcs.sh	The Synopsys* VCS* script to run the testbench.
<design_example_dir>/example_testbench/run_vcsmx.sh	The Synopsys* VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench.

Table 2. Hardware Design Example File Descriptions
File Names	Descriptions
<design_example_dir>/hardware_test_design/cpriphy_ftile_hw.qpf	Intel® Quartus® Prime project file.
<design_example_dir>/hardware_test_design/cpriphy_ftile_hw.qsf	Intel® Quartus® Prime project setting file.
<design_example_dir>/hardware_test_design/cpriphy_ftile_hw.sdc	Synopsys Design Constraints files. You can copy and modify these files for your own Intel® Agilex™ design.
<design_example_dir>/hardware_test_design/cpriphy_ftile_hw.v	Top-level Verilog HDL design example file.
<design_example_dir>/hardware_test_design/cpriphy_ftile_wrapper.sv	DUT wrapper that instantiates DUT and other testbench components.
<design_example_dir>/hardware_test_design/hwtest_sl/main_script.tcl	Main file for accessing System Console.

¹ Ignore any other simulator script in the <design_example_dir>/example_testbench/ folder.