F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
                    
                        ID
                        683281
                    
                
                
                    Date
                    10/04/2021
                
                
                    Public
                
            A newer version of this document is available. Customers should click here to go to the newest version.
2.1. Features
- Generate the design example with RS-FEC feature
- Basic packet checking capabilities including round trip latency count