CIC Intel® FPGA IP: User Guide

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ID 683246
Date 9/30/2019
Public
Document Table of Contents
Document Table of Contents x
1. About the CIC Intel® FPGA IP 2. CIC Intel® FPGA IP Getting Started 3. CIC Intel® FPGA IP Functional Description 4. CIC Intel® FPGA IP User Guide Document Archives 5. CIC Intel® FPGA IP User Guide Document Revision History
1. About the CIC Intel® FPGA IP x
1.1. DSP Intel® FPGA IP Features 1.2. CIC Intel® FPGA IP Features 1.3. DSP Intel® FPGA IP Device Family Support 1.4. DSP Intel® FPGA IP Verification 1.5. CIC Intel® FPGA IP Release Information 1.6. CIC Intel® FPGA IP Performance and Resource Utilization
2. CIC Intel® FPGA IP Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. CIC IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. CIC Intel® FPGA IP Functional Description x
3.1. Variable Rate Change Factors 3.2. Multichannel Support 3.3. CIC Output Options 3.4. FIR Filter Compensation Coefficients 3.5. CIC Intel® FPGA IP Parameters 3.6. CIC Intel® FPGA IP Interfaces and Signals
3.2. Multichannel Support x
3.2.1. Multiple Input Single Output (MISO) 3.2.2. Single Input Multiple Output (SIMO)
3.3. CIC Output Options x
3.3.1. Output Data Width 3.3.2. Output Rounding 3.3.3. Hogenauer Pruning
3.6. CIC Intel® FPGA IP Interfaces and Signals x
3.6.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 3.6.2. CIC Intel® FPGA IP Signals 3.6.3. Avalon Streaming Interface Data Transfer Timing 3.6.4. Packet Data Transfers
1. About the CIC Intel® FPGA IP
2. CIC Intel® FPGA IP Getting Started
3. CIC Intel® FPGA IP Functional Description
4. CIC Intel® FPGA IP User Guide Document Archives
5. CIC Intel® FPGA IP User Guide Document Revision History

3.1. Variable Rate Change Factors

You can optionally set minimum and maximum values for the decimator or interpolator rate change factors and enable the rate change factors to be set at run time. With these options, the CIC provides an additional rate port that you can use to specify the rate change factor.
Note: With variable rate change factors, reset the IP when you change the rate change factor, otherwise the CIC uses previous memory and register values. You cannot change the filter mode (interpolation or decimation) at run time.
Figure 7. Variable Rate Change Decimation CIC Filter Timing DiagramThe out_valid signal changes its period according to the variable rate change.
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