CIC Intel® FPGA IP: User Guide

ID 683246
Date 9/30/2019
Document Table of Contents
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3.3.3. Hogenauer Pruning

Hogenauer pruning uses truncation in intermediate stages with the retained number of bits decreasing monotonically from stage to stage. The total error introduced is still no greater than the quantization error introduced by rounding the full precision output. This technique helps to reduce the number of logic cells used by the filter and gives better performance.

The existing algorithms for computing the Hogenauer bit width growth for large N and R values are computationally expensive.

For more information about these algorithms, refer to U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, 2nd Edition, Spinger, 2004.

The CIC IP has precalculated Hogenauer pruning bit widths. The CIC does not have to calculate Hogenauer pruning bit widths if you enable Hogenauer pruning for a decimation filter.

Note: Hogenauer pruning is only available to decimation filters when the selected output data width is smaller than the full output resolution data width.