CIC Intel® FPGA IP: User Guide

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ID 683246
Date 9/30/2019
Public
Document Table of Contents
Document Table of Contents x
1. About the CIC Intel® FPGA IP 2. CIC Intel® FPGA IP Getting Started 3. CIC Intel® FPGA IP Functional Description 4. CIC Intel® FPGA IP User Guide Document Archives 5. CIC Intel® FPGA IP User Guide Document Revision History
1. About the CIC Intel® FPGA IP x
1.1. DSP Intel® FPGA IP Features 1.2. CIC Intel® FPGA IP Features 1.3. DSP Intel® FPGA IP Device Family Support 1.4. DSP Intel® FPGA IP Verification 1.5. CIC Intel® FPGA IP Release Information 1.6. CIC Intel® FPGA IP Performance and Resource Utilization
2. CIC Intel® FPGA IP Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. CIC IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. CIC Intel® FPGA IP Functional Description x
3.1. Variable Rate Change Factors 3.2. Multichannel Support 3.3. CIC Output Options 3.4. FIR Filter Compensation Coefficients 3.5. CIC Intel® FPGA IP Parameters 3.6. CIC Intel® FPGA IP Interfaces and Signals
3.2. Multichannel Support x
3.2.1. Multiple Input Single Output (MISO) 3.2.2. Single Input Multiple Output (SIMO)
3.3. CIC Output Options x
3.3.1. Output Data Width 3.3.2. Output Rounding 3.3.3. Hogenauer Pruning
3.6. CIC Intel® FPGA IP Interfaces and Signals x
3.6.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 3.6.2. CIC Intel® FPGA IP Signals 3.6.3. Avalon Streaming Interface Data Transfer Timing 3.6.4. Packet Data Transfers
1. About the CIC Intel® FPGA IP
2. CIC Intel® FPGA IP Getting Started
3. CIC Intel® FPGA IP Functional Description
4. CIC Intel® FPGA IP User Guide Document Archives
5. CIC Intel® FPGA IP User Guide Document Revision History

3.5. CIC Intel® FPGA IP Parameters

Table 7.  CIC Intel® FPGA IP Parameters
Parameter Value Description
Filter Specification
Filter type Decimator, Interpolator Selects a decimator or interpolator.
Number of stages 1 to 12 Specifies the required number of stages.
Differential delay 1, 2 Specifies the differential delay in cycles.
Enable variable rate change factor On or Off Turn on to enable a variable rate change factor that you can change at runtime. When this option is on, the Rate change factor parameter is not available but you can specify minimum and maximum values.
Rate change factor 2 to 32000 Specifies the rate change factor.
Number of interfaces 1 to 128 Specifies the number of MISO inputs or SIMO outputs The product of the Number of interfaces and the Number of channels per interface must be no more than 1024.
Number of channels per interface 1 to 1024 Specifies the number of channels per interface. The product of the Number of interfaces and the Number of channels per interface must be no more than 1024
Interface Specification
Input data width 1 to 32 Specifies the input data width in bits.
Output Rounding Options None, Truncation, Convergent rounding, Rounding up, Saturation, Hogenauer pruning Selects the required rounding output mode. Select None for full output resolution. The saturation limit is the maximum value for overflow or the minimum value for negative overflow. Hogenauer pruning is available only when a Decimator filter type is selected in the Architecture page.
Output data width 1 to calculated maximum data width Specifies the output data width in bits.
implementation Options
Integrator data storage Logic Element, Memory Selects whether to implement the integrator data storage as logic elements or memory. The Memory option is available for integrator data storage when the Number of channels per interface is greater than 4.
RAM type of integrator data storage AUTO, M9K, M10K, M20K, M144K, MLAB When you select Memory, you can select the RAM type for integrator data storage. The Memory option is available for integrator data storage when the Number of channels per interface is greater than 4.
Differentiator data storage Logic Element, Memory Selects whether to implement the differentiator data storage as logic elements or memory. The Memory option is available for differentiator data storage when the product of the Differential delay, Number of channels per interface and Number of interfaces is greater than 4.
RAM type of differentiator data storage AUTO, M9K, M10K, M20K, M144K, MLAB When you select Memory, you can select the RAM type for differentiator data storage. The options available depend on the target device family. When AUTO is selected, the Intel® Quartus® Prime software automatically selects the optimum RAM type for the currently selected device family.
Pipeline stages per integrator — Enter the pipeline stages per integrator. This option is available when the Number of channels per interface is greater than or equal to 2 (or greater than or equal to 6, when you select the Memory option for integrator data storage).

Use this option for multichannel designs that have large input bit width and require high fMAX, but not for designs targeting Cyclone devices.

Pipeline stages per integrator 1 to 4 Specifies the number of pipeline stages used by each integrator. Adding additional integrators can improve fMAX but increases the resource utilization.

The maximum number of pipeline stages depends on the number of channels and whether you select Memory or Logic Cells for integrator data storage. For Memory, the maximum number of pipeline stages equals the number of channels minus 5. For Logic Cells, the maximum number of pipeline stages equals the number of channels.

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