CIC Intel® FPGA IP: User Guide

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ID 683246
Date 9/30/2019
Public
Document Table of Contents
Document Table of Contents x
1. About the CIC Intel® FPGA IP 2. CIC Intel® FPGA IP Getting Started 3. CIC Intel® FPGA IP Functional Description 4. CIC Intel® FPGA IP User Guide Document Archives 5. CIC Intel® FPGA IP User Guide Document Revision History
1. About the CIC Intel® FPGA IP x
1.1. DSP Intel® FPGA IP Features 1.2. CIC Intel® FPGA IP Features 1.3. DSP Intel® FPGA IP Device Family Support 1.4. DSP Intel® FPGA IP Verification 1.5. CIC Intel® FPGA IP Release Information 1.6. CIC Intel® FPGA IP Performance and Resource Utilization
2. CIC Intel® FPGA IP Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. CIC IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. CIC Intel® FPGA IP Functional Description x
3.1. Variable Rate Change Factors 3.2. Multichannel Support 3.3. CIC Output Options 3.4. FIR Filter Compensation Coefficients 3.5. CIC Intel® FPGA IP Parameters 3.6. CIC Intel® FPGA IP Interfaces and Signals
3.2. Multichannel Support x
3.2.1. Multiple Input Single Output (MISO) 3.2.2. Single Input Multiple Output (SIMO)
3.3. CIC Output Options x
3.3.1. Output Data Width 3.3.2. Output Rounding 3.3.3. Hogenauer Pruning
3.6. CIC Intel® FPGA IP Interfaces and Signals x
3.6.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 3.6.2. CIC Intel® FPGA IP Signals 3.6.3. Avalon Streaming Interface Data Transfer Timing 3.6.4. Packet Data Transfers
1. About the CIC Intel® FPGA IP
2. CIC Intel® FPGA IP Getting Started
3. CIC Intel® FPGA IP Functional Description
4. CIC Intel® FPGA IP User Guide Document Archives
5. CIC Intel® FPGA IP User Guide Document Revision History

3.6.2. CIC Intel® FPGA IP Signals

Table 9.  CIC Intel® FPGA IP Signals
Signal Direction Description
av_st_in_data Input In Platform Designer systems, this Avalon streaming-compliant data bus includes all the Avalon steaming input data signals. For multi-interface designs Interface 0 is in the MSB; Interface N is the LSB.
clk Input Clock signal for all internal registers.
clken Input Optional top-level clock enable.
reset_n Input Active low reset signal. You must always reset the CIC IP before receiving data. If not, the CIC filter may produce unexpected results because of feedback signals.
in_data Input Sample input. For multiple input cases, the input data ports are in0_data, in1_data, and so on.
in_endofpacket Input Indicates the end of the incoming sample group. For N channels, the end of packet signal must be high when the sample belonging to the last channel, channel N-1, is presented at in_data.
in_error Input Error signal indicating Avalon streaming protocol violations on input side:
  • 00: No error
  • 01: Missing start of packet
  • 10: Missing end of packet
  • 11: Unexpected end of packet

    Other types of error are also marked as 11.

in_ready Output Indicates when the IP can accept data.
in_startofpacket Input Indicates the start of the incoming sample group. The start of packet is interpreted as a sample from channel 0.
in_valid Input Asserted when data at in_data is valid. When in_valid is not asserted, processing is stopped until valid is re-asserted. If clken is 0, in_valid is not be asserted.
av_st_out_data Output In Platform Designer systems, this Avalon streaming-compliant data bus includes all the Avalon streaming output data signals. For multi-interface designs Interface 0 is in the MSB; Interface N is the LSB.
out_channel Output Specifies the channel whose result is presented at out_data.
out_data Output Filter output. The data width depends on the parameter settings. For multiple output cases, the output data ports are named as out0_data, out1_data, and so on.
out_endofpacket Output Marks the end of the outgoing result group. If '1', a result corresponding to channel N-1 is output, where N is the number of channels.
out_error Output Error signal indicating Avalon streaming protocol violations on source side:
  • 00: No error
  • 01: Missing start of packet
  • 10: Missing end of packet
  • 11: Unexpected end of packet

    Other types of errors may also be marked as 11.

out_ready Input Asserted by the downstream module if it can accept data.
out_startofpacket Output Marks the start of the outgoing result group. If '1', a result corresponding to channel 0 is output.
out_valid Output Asserted by the IP when there is valid data to output.
rate Input This signal is available when the variable rate change factor option is enabled. You can use it to change the decimation or interpolation rate during run time. It has the size Ceil(log2(maximum rate)).
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