CIC Intel® FPGA IP: User Guide

Download PDF
ID 683246
Date 9/30/2019
Public
Document Table of Contents
Document Table of Contents x
1. About the CIC Intel® FPGA IP 2. CIC Intel® FPGA IP Getting Started 3. CIC Intel® FPGA IP Functional Description 4. CIC Intel® FPGA IP User Guide Document Archives 5. CIC Intel® FPGA IP User Guide Document Revision History
1. About the CIC Intel® FPGA IP x
1.1. DSP Intel® FPGA IP Features 1.2. CIC Intel® FPGA IP Features 1.3. DSP Intel® FPGA IP Device Family Support 1.4. DSP Intel® FPGA IP Verification 1.5. CIC Intel® FPGA IP Release Information 1.6. CIC Intel® FPGA IP Performance and Resource Utilization
2. CIC Intel® FPGA IP Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. CIC IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. CIC Intel® FPGA IP Functional Description x
3.1. Variable Rate Change Factors 3.2. Multichannel Support 3.3. CIC Output Options 3.4. FIR Filter Compensation Coefficients 3.5. CIC Intel® FPGA IP Parameters 3.6. CIC Intel® FPGA IP Interfaces and Signals
3.2. Multichannel Support x
3.2.1. Multiple Input Single Output (MISO) 3.2.2. Single Input Multiple Output (SIMO)
3.3. CIC Output Options x
3.3.1. Output Data Width 3.3.2. Output Rounding 3.3.3. Hogenauer Pruning
3.6. CIC Intel® FPGA IP Interfaces and Signals x
3.6.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 3.6.2. CIC Intel® FPGA IP Signals 3.6.3. Avalon Streaming Interface Data Transfer Timing 3.6.4. Packet Data Transfers
1. About the CIC Intel® FPGA IP
2. CIC Intel® FPGA IP Getting Started
3. CIC Intel® FPGA IP Functional Description
4. CIC Intel® FPGA IP User Guide Document Archives
5. CIC Intel® FPGA IP User Guide Document Revision History

3.4. FIR Filter Compensation Coefficients

CIC filters have a low-pass filter characteristic. Three parameters (the rate change factor R, the number of stages N, and the differential delay M) allow you to change the passband characteristics and aliasing or imaging rejection.

Typically, decimation or interpolation filtering applications require flat passband and narrow transition region filter performance. However, the CIC filter has drooping passband gains and wide transition regions. To overcome these problems connect the decimation or interpolation CIC filter to a compensation FIR filter, which narrows the output bandwidth and flattens the passband gain.

Figure 10. Using a CIC Compensation FIR Filter

You can use a frequency sampling method to determine the coefficients of a FIR filter that equalizes the undesirable passband droop of the CIC and construct an ideal frequency response.

Determine the ideal frequency response by sampling the normalized magnitude response of the CIC filter before inverting the response.

Generally, only equalize the response in the passband, but you can sample further than the passband to fine tune the cascaded response of the filter chain.

The CIC IP generates a MATLAB script <variation_name>_fir_comp_coeff.m in the project directory. You can run this script in MATLAB to generate FIR coefficients that provide appropriate passband equalization. The generated coefficients are saved in a text file, for use by the FIR IP.

The MATLAB script requires the following parameters for the compensation FIR filter:

  • L: FIR filter length, which is same as the number of taps or the number of coefficients
  • F S : FIR filter sample rate in Hz before decimation/interpolation
  • F C: FIR filter cutoff frequency in Hz
  • B: Coefficient bit width if coefficients are written in fixed-point numbers
    Figure 11. CIC and Compensation Filter Responses
Related Information
Level Two Title