CIC Intel® FPGA IP: User Guide

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ID 683246
Date 9/30/2019
Public
Document Table of Contents
Document Table of Contents x
1. About the CIC Intel® FPGA IP 2. CIC Intel® FPGA IP Getting Started 3. CIC Intel® FPGA IP Functional Description 4. CIC Intel® FPGA IP User Guide Document Archives 5. CIC Intel® FPGA IP User Guide Document Revision History
1. About the CIC Intel® FPGA IP x
1.1. DSP Intel® FPGA IP Features 1.2. CIC Intel® FPGA IP Features 1.3. DSP Intel® FPGA IP Device Family Support 1.4. DSP Intel® FPGA IP Verification 1.5. CIC Intel® FPGA IP Release Information 1.6. CIC Intel® FPGA IP Performance and Resource Utilization
2. CIC Intel® FPGA IP Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. CIC IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. CIC Intel® FPGA IP Functional Description x
3.1. Variable Rate Change Factors 3.2. Multichannel Support 3.3. CIC Output Options 3.4. FIR Filter Compensation Coefficients 3.5. CIC Intel® FPGA IP Parameters 3.6. CIC Intel® FPGA IP Interfaces and Signals
3.2. Multichannel Support x
3.2.1. Multiple Input Single Output (MISO) 3.2.2. Single Input Multiple Output (SIMO)
3.3. CIC Output Options x
3.3.1. Output Data Width 3.3.2. Output Rounding 3.3.3. Hogenauer Pruning
3.6. CIC Intel® FPGA IP Interfaces and Signals x
3.6.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 3.6.2. CIC Intel® FPGA IP Signals 3.6.3. Avalon Streaming Interface Data Transfer Timing 3.6.4. Packet Data Transfers
1. About the CIC Intel® FPGA IP
2. CIC Intel® FPGA IP Getting Started
3. CIC Intel® FPGA IP Functional Description
4. CIC Intel® FPGA IP User Guide Document Archives
5. CIC Intel® FPGA IP User Guide Document Revision History

5. CIC Intel® FPGA IP User Guide Document Revision History

Date Intel® Quartus® Prime Version IP Version Changes
2019.09.30 19.3 19.3 Changed Intel Stratix 10 device support to final.
November 2017 17.1 2017.11.06
  • Removed product ID and vendor ID.
  • Added support for Intel® Cyclone® 10 and Intel® Stratix® 10 devices
  • Corrected av_st_in_data signal direction to input.
2014.12.15   14.1
  • Added final support for Arria 10 devices
  • Reordered parameters tables to match wizard
August 2014   14.0 Arria 10 Edition
  • Added support for Arria 10 devices.
  • Added new av_st_in_data and av_st_out_data bus descriptions.
  • Added Arria 10 generated files description.
  • Removed table with generated file descriptions.
June 2014   14.0
  • Removed support for Cyclone III and Stratix III devices
  • Added instructions for using IP Catalog
November 2013   13.1
  • Removed support for the following devices:
    • Arria
    • Cyclone II
    • HardCopy II, HardCopy III, and HardCopy IV
    • Stratix, Stratix II, Stratix GX, and Stratix II GX
  • Added full support for the following devices:
    • Arria V
    • Stratix V
November 2012   12.1 Added support for Arria V GZ devices.
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