CIC Intel® FPGA IP: User Guide

ID 683246
Date 9/30/2019
Document Table of Contents
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3.6.4. Packet Data Transfers

A beat is the transfer of one unit of data between a source and sink interface. This unit of data may consist of one or more symbols and makes it is possible to support modules that convey more than one piece of information about each valid cycle.

Packet data transfers are used for multichannel transfers. Two additional signals (startofpacket and endofpacket) are defined to implement the packet transfer.

The multiple symbols per beat scenario applies to both the sink interface on MISO CIC filters and the source interface of SIMO CIC filters. All other interfaces operate with a single symbol per beat, but the interfaces also support multiple channels using packets.

Figure 13. Packet Data Transfer Four symbols are transferred on each beat. The data transfer occurs on cycles 1, 2, 4, and 5, when both ready and valid are asserted.

During cycle 1, the CIC IP asserts startofpacket, and transfers the first four bytes of packet. During cycle 5, the CIC IP asserts endofpacket indicating that this is the end of the packet. The channel signal indicates the channel index associated with the data. For example, on cycle 1, the data D0, D1, D2, and D3 associated with channel 0 are available.