Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 8/03/2023

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Document Table of Contents Set Clock Groups (set_clock_groups)

The Set Clock Groups (set_clock_groups) constraint allows you to specify which clocks in the design are unrelated. By default, the Timing Analyzer assumes that all clocks with a common base or parent clock are related, and that all transfers between those clock domains are valid for timing analysis. You can exclude transfers between specific clock domains from timing analysis by cutting clock groups.

Conversely, clocks without a common parent or base clock are always unrelated, but timing analysis includes the transfers between such clocks, unless those clocks are in different clock groups (or if all of their paths are cut with false path constraints).

You define the clock signals to include in each Group (-group), then specify the relationship between different groups, and then specify whether the groups are Logically exclusive (-logically_exclusive), Physically exclusive (-physically_exclusive, or Asynchronous ( -asynchronous) from one another.

set_clock_groups -asynchronous -group {<clock1>...<clockn>} ... \
    -group {<clocka>...<clockn>}
  • -logically_exclusive—defines clocks that are logically exclusive and not active at the same time, such as multiplexed clocks
  • -physically_exclusive—defines clocks that that cannot be physically on the device at the same time.
  • -asynchronous—defines completely unrelated clocks that have different ideal clock sources. This flag means the clocks are both switching, but not in a way that can synchronously pass data.

For example, if there are paths between an 8ns clock and 10ns clock, even if the clocks are completely asynchronous, the Timing Analyzer attempts to meet a 2ns setup relationship between these clocks, unless you specify that they are not related.

The following shows example constraints for a clock mux with two inputs, with multi-rate clocks, and the appropriate combinations of logical and physical exclusivity:

# First profile
create_clock -name clk_a1 -period 10 [get_ports clk_a]
create_clock -name clk_b1 -period 20 [get_ports clk_b]

# Second profile
create_clock -name clk_a2 -period 100 [get_ports clk_a] -add
create_clock -name clk_b2 -period 200 [get_ports clk_b] -add

# Mark base clocks as asynchronous to each other
set_clock_groups -asynchronous -group {clk_a?} -group {clk_b?}

# Define muxed clocks for each profile
set muxout [get_pins -compatibility_mode {mux*|combout}]
foreach profile {1 2} {
     set mux_clk_a "mux_clk_a${profile}"
     set mux_clk_b "mux_clk_b${profile}"
     create_generated_clock -name $mux_clk_a -source [get_ports clk_a] \
          -master_clock "clk_a${profile}" $muxout -add
     create_generated_clock -name $mux_clk_b -source [get_ports clk_b] \
          -master_clock "clk_b${profile}" $muxout -add
     # Mark each muxed clock as logically exclusive to each other
     set_clock_groups -logically_exclusive -group $mux_clk_a \
          -group $mux_clk_b

# Mark profile clocks as physically exclusive to each other
# (Do this after defining the derived clocks so they get cut too)
set_clock_groups -physically_exclusive -group {*clk_?1} \
     -group {*clk_?2}
Figure 92. Example Constraints Design Topology

Although the Set Clock Groups dialog box only permits two clock groups, you can specify an unlimited number of -group {<group of clocks>} options in the .sdc file. If you omit an unrelated clock from the assignment, the Timing Analyzer acts conservatively and analyzes that clock in context with all other domains to which the clock connects.

The Timing Analyzer does not currently analyze crosstalk explicitly. Instead, the timing models use extra guard bands to account for any potential crosstalk-induced delays. The Timing Analyzer treats the -asynchronous and -exclusive options the same for crosstalk-related analysis, but treats asynchronous and exclusive clock groups differently for things like max skew reporting and synchronizer detection.

A clock cannot be within multiple groups (-group) in a single assignment; however, you can have multiple set_clock_groups assignments.

Another way to cut timing between clocks is to use set_false_path. To cut timing between sys_clk and dsp_clk, you can use:

set_false_path -from [get_clocks sys_clk] -to [get_clocks dsp_clk]
set_false_path -from [get_clocks dsp_clk] -to [sys_clk]

This technique is effective if there are only a few clocks, but can become unmanageable with a large number of constraints. In a simple design with three PLLs that have multiple outputs, the set_clock_groups command can cut timing between clocks with less than ten lines, but the set_false_path command may require more than 50 lines.