Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 8/03/2023
Document Table of Contents Constraining Design Partition Ports

You can assign clock definitions and SDC exceptions to design partition ports. The block-based design and partial reconfiguration design flows require the use of design partitions.

The Compiler represents design partition ports in your timing netlist as combinational nodes with persistent names that the Compiler cannot optimize away. You can safely refer to these ports as clock sources or -through points in SDC constraints. You can also use design partition port names as -to and -from points in the report_path command.

If a port on partition_a has the name clk_divide, then the SDC constraint is:

create_generated_clock –source clock -divide_by 2 \

If a set of ports on partition_b has the name data_input[0..7], then the SDC constraint is:

set_multicycle_path –from top|partition_a|data_reg* \
     -through top|partition_b|data_input* 2

You can use multiple -through clauses. This technique allows you to specify paths that go through output ports of one design partition, and then through the input ports of another, downstream design partition.

To add constraints to partition ports:

  1. Run Analysis & Synthesis or run full compilation on a design containing design partitions.
  2. To open the RTL Viewer and locate the partition ports of interest, click Tools > Netlist Viewers > RTL Viewer.
  3. Using the same names as the RTL Viewer, add clock and other SDC constraints to the .sdc file for your project. You can use wildcards to refer to more than one port.
  4. Recompile the design to apply the new definitions and constraints.

    Aside from block-based and PR flows, this technique also aids in emulation of ASICs using FPGAs. In this type of design, clock networks often span multiple hierarchies of partitions. Typically, designers remove the clock-dividing circuitry from the netlist, since they cannot easily emulate this circuitry on Intel FPGAs. For such clock networks, this technique allows you to define different versions of the clock signal in places where the circuitry is removed.

    You must design and place your partitions strategically, and then define the appropriate ports on these partitions. Ensure that your ports and partitions coincide with the part of the clock network which contains the special circuitry. You can manually edit the emulated ASIC netlist to annotate appropriate clock definitions and clock relationships. You can also use this technique in any projects where arbitrary locations on paths require constrained timing or defined clock sources.

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