Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 8/03/2023

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3.6.3. Modifying Iterative Constraints

Iteratively modify .sdc constraints and reanalyze the timing results to ensure that you have complete constraints for your design.
  1. Click Tools > Timing Analyzer.
  2. Generate the reports you want to analyze. Double-click Report All Summaries under Macros to generate setup, hold, recovery, and removal summaries, summaries for supported reports, and a list of all the defined clocks in the design. These summaries cover all paths you constrain in your design. Whenever modifying or correcting constraints, generate the Constraint Diagnostic reports to identify unconstrained parts of your design, or ignored constraints.
  3. Analyze the results in the reports. When you are modifying constraints, rerun the reports to find any unexpected results. For example, a cross-domain path might indicate that you forgot to cut a transfer by including a clock in a clock group.
  4. Create or edit the appropriate constraints in your .sdc file and save the file.
  5. Double-click Reset Design in the Tasks pane. This removes all constraints from your design. Removing all constraints from your design allows rereading the .sdc files, including your changes.
  6. Regenerate the reports you want to analyze.
  7. Reanalyze the results.
  8. Repeat steps 4-7 as necessary.

This method performs timing analysis using new constraints, without any change to logic placement. While the Fitter uses the original constraints for place and route, the Timing Analyzer applies the new constraints. If you see any failing timing against the new constraints, run place-and-route again.