Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 8/03/2023

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Document Table of Contents False Paths (set_false_path)

The Set False Path (set_false_path) constraint allows you to exclude a path from timing analysis, such as test logic or any other path not relevant to the circuit's operation. You can specify the source (-from), common through elements (-thru), and destination (-to) elements of that path.

The following SDC command makes false path exceptions from all registers starting with A, to all registers starting with B:

set_false_path -from [get_pins A*] -to [get_pins B*]

You can specify either a point-to-point or clock-to-clock path as a false path. A false path's -from and -to targets can be either nodes or clocks. However, the -thru targets can only be combinational nodes. For example, you can specify a false path for a static configuration register that writes once during power-up initialization, but does not change state again.

Although signals from static configuration registers often cross clock domains, you may not want to make false path exceptions to a clock-to-clock path, because some data may transfer across clock domains. However, you can selectively make false path exceptions from the static configuration register to all endpoints.

The Timing Analyzer assumes all clocks are related unless you specify otherwise. Use clock groups to more efficiently make false path exceptions between clocks, rather than writing multiple set_false_path exceptions between each clock transfer you want to eliminate.