Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 8/03/2023
Document Table of Contents

3.6.1. Recommended Initial SDC Constraints

Include the following basic SDC constraints in your initial .sdc file.
The following example shows application of the recommended initial SDC constraints for a simple dual-clock design:
create_clock -period 20.00 -name adc_clk [get_ports adc_clk]
create_clock -period 8.00 -name sys_clk [get_ports sys_clk]


Note: Only Intel® Arria® 10 and Intel® Cyclone® 10 GX devices support the Derive PLL Clocks (derive_pll_clocks) constraint. For all other supported devices, the Timing Analyzer automatically derives PLL clocks from constraints bound to the related IP.

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