2.2.1. Timing Path and Clock Analysis 2.2.2. Clock Setup Analysis 2.2.3. Clock Hold Analysis 2.2.4. Recovery and Removal Analysis 2.2.5. Multicycle Path Analysis 2.2.6. Metastability Analysis 2.2.7. Timing Pessimism 2.2.8. Clock-As-Data Analysis 2.2.9. Multicorner Timing Analysis 2.2.10. Time Borrowing
3.1. Timing Analysis Flow 3.2. Step 1: Specify Timing Analyzer Settings 3.3. Step 2: Specify Timing Constraints 3.4. Step 3: Run the Timing Analyzer 3.5. Step 4: Analyze Timing Reports 3.6. Applying Timing Constraints 3.7. Timing Analyzer Tcl Commands 3.8. Timing Analysis of Imported Compilation Results 3.9. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History 3.10. Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
188.8.131.52. Report Fmax Summary 184.108.40.206. Report Timing 220.127.116.11. Report Timing By Source Files 18.104.22.168. Report Data Delay 22.214.171.124. Report Net Delay 126.96.36.199. Report Clocks and Clock Network 188.8.131.52. Report Clock Transfers 184.108.40.206. Report Metastability 220.127.116.11. Report CDC Viewer 18.104.22.168. Report Asynchronous CDC 22.214.171.124. Report Logic Depth 126.96.36.199. Report Neighbor Paths 188.8.131.52. Report Register Spread 184.108.40.206. Report Route Net of Interest 220.127.116.11. Report Retiming Restrictions 18.104.22.168. Report Register Statistics 22.214.171.124. Report Pipelining Information 126.96.36.199. Report Time Borrowing Data 188.8.131.52. Report Exceptions and Exceptions Reachability 184.108.40.206. Report Bottlenecks
3.6.1. Recommended Initial SDC Constraints 3.6.2. SDC File Precedence 3.6.3. Modifying Iterative Constraints 3.6.4. Using Entity-bound SDC Files 3.6.5. Creating Clocks and Clock Constraints 3.6.6. Creating I/O Constraints 3.6.7. Creating Delay and Skew Constraints 3.6.8. Creating Timing Exceptions 3.6.9. Using Fitter Overconstraints 3.6.10. Example Circuit and SDC File
220.127.116.11.1. Default Multicycle Analysis 18.104.22.168.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 22.214.171.124.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 126.96.36.199.4. Same Frequency Clocks with Destination Clock Offset 188.8.131.52.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 184.108.40.206.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset 220.127.116.11.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 18.104.22.168.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
22.214.171.124. Report Neighbor Paths
The Timing Analyzer's Reports > Design Metrics > Report Neighbor Paths... command helps you to determine the root cause of critical paths (for example, high logic level, retiming limitation, sub-optimal placement, I/O column crossing, hold fix-up, time borrowing, or others). The equivalent scripting command is report_design_metrics -neighbor_paths.
Figure 61. Report Neighbor Paths Report
Report Neighbor Paths reports the most timing-critical paths in the design, including associated slack, additional path summary information, and path bounding boxes. Report Neighbor Paths shows the most timing-critical Path Before and Path After each critical Path. You can optionally view multiple before and after paths. Retiming or logic balancing of the Path can simplify timing closure if there is negative slack on the Path, but positive slack on the Path Before or Path After.
|Clocks||From Clock and To Clock filter paths in the report to show only the launching or latching clocks you specify.|
|Targets||Specifies the target node for From Clock and To Clock to report neighbor paths with only those endpoints. Specify an I/O or register name or I/O port for this option. The field also supports wildcard characters. When the From, To, or Through boxes are empty, the Timing Analyzer assumes all possible targets in the device. The Through option limits the report for paths that pass through combinatorial logic, or a particular pin on a cell.|
|Analysis type||The Analysis type options are Setup, Hold, Recovery, or Removal. The Timing Analyzer reports the results for the type of analysis you select.|
|Paths||Specifies the number of paths to display by endpoint and slack level. The default value for Report number of paths is 10, otherwise, the report can be very long. Enable Pairs only to list only one path for each pair of source and destination. Limit further with Maximum number of paths per endpoints. You can also filter paths by entering a value in the Maximum slack limit field.|
|Report Number of Neighbor Paths||Specifies the number of neighbor paths to report, allowing you to view a number of the top adjacent paths entering the critical path, and the top paths exiting the critical path.|
|Report panel name||Specifies the name of the report panel. You can optionally enable File name to write the information to a file. If you append .htm or .html as a suffix, the Timing Analyzer produces the report as HTML. If you enable File name, you can Overwrite or Append the file with latest data.|
|Tcl command||Displays the Tcl syntax that corresponds with the GUI options you select. You can copy the command from the Console into a Tcl file.|
|Extra Info||Specifies extra info.|
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