Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 4/03/2023
Document Table of Contents

2.2.8. Clock-As-Data Analysis

The majority of FPGA designs contain simple connections between any two nodes, known as either a data path or a clock path.

A data path is a connection between the output of a synchronous element to the input of another synchronous element.

A clock is a connection to the clock pin of a synchronous element. However, for more complex FPGA designs, such as designs that use source-synchronous interfaces, this simplified view is no longer sufficient. The Timing Analyzer performs clock-as-data analysis in circuits with elements such as clock dividers and DDR source-synchronous outputs.

You can treat the connection between the input clock port and output clock port as a clock path or a data path. Simplified Source Synchronous Output shows a design where the path from port clk_in to port clk_out is both a clock and a data path. The clock path is from the port clk_in to the register reg_data clock pin. The data path is from port clk_in to the port clk_out.

Figure 32. Simplified Source Synchronous Output

With clock-as-data analysis, the Timing Analyzer provides a more accurate analysis of the path based on user constraints. In the clock path analysis, the Timing Analyzer includes any phase shift associated with the phase-locked loop (PLL). For the data path analysis, the Timing Analyzer includes any phase shift associated with the PLL, rather than ignoring the phase shift.

The clock-as-data analysis also applies to internally generated clock dividers. In the following figure, the waveforms are for the inverter feedback path, analyzed during timing analysis. The output of the divider register determines the launch time, and the clock port of the register determines the latch time.

Figure 33. Clock Divider

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