Nios II Custom Instruction User Guide

ID 683242
Date 4/27/2020
Document Table of Contents
Give Feedback Output of the CRC Design Example Software Run on a Cyclone V E FPGA Development Kit using the Intel® Quartus® Prime Software v15.1.

Comparison between software and custom instruction CRC32 ****************************************************************************** 
System specification 
System clock speed = 50 MHz 
Number of buffer locations = 32 
Size of each buffer = 256 bytes 
Initializing all of the buffers with pseudo-random data
Initialization completed 
Running the software CRC 
Running the optimized software CRC 
Running the custom instruction CRC 
Validating the CRC results from all implementations 
All CRC implementations produced the same results 
Processing time for each implementation 
Software CRC = 34 ms
Optimized software CRC = 19 ms 
Custom instruction CRC = 00 ms 
Processing throughput for each implementation 
Software CRC = 2978 Mbps 
Optimized software CRC = 32768 Mbps 
Custom instruction CRC = 949 Mbps 
Speedup ratio 
Custom instruction CRC vs software CRC = 68 
Custom instruction CRC vs optimized software CRC = 39
Optimized software CRC vs software CRC = 1