Nios II Custom Instruction User Guide

ID 683242
Date 4/27/2020
Document Table of Contents

2.1.3. Extended Custom Instructions

An extended custom instruction allows a single custom logic block to implement several different operations.

Extended custom instruction components occupy multiple select indices. The selection indices are determined when the custom instruction hardware block is instantiated in the system using Platform Designer.

Extended custom instructions use an extension index to specify which operation the logic block performs. The extension index can be up to eight bits wide, allowing a single custom logic block to implement as many as 256 different operations.

The following block diagram shows an extended custom instruction with bit-swap, byte-swap, and half-word swap operations.

Figure 7. Extended Custom Instruction with Swap Operations

The custom instruction in the preceding figure performs swap operations on data received at the dataa port. The instruction hardware uses the two bit wide n port to select the output from a multiplexer, determining which result is presented to the result port.

Note: This logic is just a simple example, using a multiplexer on the output. You can implement function selection based on an extension index in any way that is appropriate for your application.

Extended custom instructions can be combinational or multicycle custom instructions. To implement an extended custom instruction, add an n port to your custom instruction logic. The bit width of the n port is a function of the number of operations the custom logic block can perform.

An extended custom instruction block occupies several contiguous selection indices. When the block is instantiated, Platform Designer determines a base selection index. When the Nios II processor decodes a custom instruction, the custom hardware block's n port decodes the low-order bits of the selection index. Thus, the extension index extends the base index to produce the complete selection index.

For example, suppose the custom instruction block in Figure 7 is instantiated in a Nios II system with a base selection index of 0x1C. In this case, individual swap operations are selected with the following selection indices:

  • 0x1C—Bit swap
  • 0x1D—Byte swap
  • 0x1E—Half-word swap
  • 0x1F—reserved

Therefore, if n is <m> bits wide, the extended custom instruction component occupies 2 <m> select indices.

For example, the custom instruction illustrated above occupies four indices, because n is two bits wide. Therefore, when this instruction is implemented in a Nios II system, 256 - 4 = 252 available indices remain.