1. Nios II Custom Instruction Overview
2. Custom Instruction Hardware Interface
3. Custom Instruction Software Interface
4. Design Example: Cyclic Redundancy Check
5. Introduction to Nios® II Floating Point Custom Instructions
6. Nios II Floating Point Hardware 2 Component
7. Nios® II Floating Point Hardware (FPH1) Component
8. Document Revision History for Nios II Custom Instruction User Guide
4.1.1. Setting up the Environment for the CRC Example Design
4.1.2. Opening the Component Editor
4.1.3. Specifying the Custom Instruction Component Type
4.1.4. Displaying the Custom Instruction Block Symbol
4.1.5. Adding the CRC Custom Instruction HDL Files
4.1.6. Configuring the Custom Instruction Parameter Type
4.1.7. Setting Up the CRC Custom Instruction Interfaces
4.1.8. Configuring the Custom Instruction Signal Type
4.1.9. Saving and Adding the CRC Custom Instruction
4.1.10. Generating and Compiling the CRC Example System
6.1. Overview of the Floating Point Hardware 2 Component
6.2. Floating Point Hardware 2 IEEE 754 Compliance
6.3. IEEE 754 Exception Conditions with FPH2
6.4. Floating Point Hardware 2 Operations
6.5. Building the FPH2 Example Hardware
6.6. Building the FPH2 Example Software
6.7. FPH2 Implementation of GCC Options
6.8. Nios II FPH2 and the Newlib Library
6.9. C Macros for round(), fmins(), and fmaxs()
5.2.1. Unit in the Last Place
Unit in the last place (ULP) represents the value 2-23, which is approximately 1.192093e-07. The ULP is the distance between the closest straddling floating point numbers a and b (a ≤ x ≤ b, a ≠ b), assuming that the exponent range is not upper-bounded. The IEEE Round-to-Nearest modes produce results with a maximum error of one-half ULP. The other IEEE rounding modes (Round-to-Zero, Round-to-Positive-Infinity, and Round-to-Negative-Infinity) produce results with a maximum error of one ULP.