Nios II Custom Instruction User Guide

ID 683242
Date 4/27/2020
Public
Document Table of Contents
Give Feedback

7.1. Creating the FPH1 Example Hardware

The requirements for building the hardware are as follows:

  • Intel® Quartus® Prime software , installed on a Windows or Linux computer
  • A JTAG download cable compatible with your target hardware, for example, an Intel® FPGA Download Cable
  • A development board that includes the following devices:
    • An Intel FPGA large enough to support the Nios II processor core, hold the target design, and leave enough unused logic elements to support the FPH1 custom instructions.
    • An oscillator that drives a constant clock frequency to an FPGA pin. The maximum frequency depends on the speed grade of the FPGA.
    • A JTAG connection to the FPGA that provides a programming interface and communication link to the Nios II system.
  • A Nios II target design that includes the following components:
    • Nios II processor
    • JTAG UART
    • Performance counter with at least 2 simultaneously-measured sections
    • 128 KB of on-chip or external memory
    • System timer
    • System ID peripheral

Intel provides several working Nios II reference designs which you can use as a starting point for your own designs. After installing the Nios II EDS, refer to the <Nios  II EDS install path> /examples/verilog or the <Nios  II EDS install path> /examples/vhdl directory. Demonstration applications are also available in newer development kit installations.