Nios II Custom Instruction User Guide

ID 683242
Date 4/27/2020
Public
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4.1.5. Adding the CRC Custom Instruction HDL Files

To specify the synthesis HDL files for your custom instruction, you browse to the HDL logic definition files in the design example.

To specify the synthesis files, follow these steps:

  1. Click Next to display the Files tab.
  2. Under Synthesis Files, click Add Files.
  3. Browse to <project_dir> /crc_hw, the location of the HDL files for this design example.
  4. Select the CRC_Custom_Instruction.v and CRC_Component.v files and click Open.
    Figure 14. Browsing to Custom Instruction HDL Files
    Note: The Intel® Quartus® Prime Analysis and Synthesis program checks the design for errors when you add the files. Confirm that no error message appears.
  5. Open the File Attributes dialog box by double-clicking the Attributes column in the CRC_Custom_Instruction.v line.
    Figure 15. File Attributes Dialog Box
  6. In the File Attributes dialog box, turn on the Top-level File attribute, as shown in the figure above. This attribute indicates that CRC_Custom_Instruction.v is the top-level HDL file for this custom instruction.
  7. Click OK.
    Note: The Intel® Quartus® Prime Analysis and Synthesis program checks the design for errors when you select a top-level file. Confirm that no error message appears.
  8. Click Analyze Synthesis Files to synthesize the top-level file.
  9. To simulate the system with the ModelSim* - Intel® FPGA Edition simulator, you can add your simulation files under Verilog Simulation Files or VHDL Simulation Files in the in the Files tab.