Nios II Custom Instruction User Guide

ID 683242
Date 4/27/2020
Public
Document Table of Contents
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2.1.1.2. Combinational Custom Instruction Timing

The processor presents the input data on the dataa and datab ports on the rising edge of the processor clock. The processor reads the result port on the rising edge of the following processor clock cycle.

Figure 4. Combinational Custom Instruction Timing Diagram