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1.1. Intel® Stratix® 10 DX Devices
1.2. Intel® Stratix® 10 DX Features Summary
1.3. Intel® Stratix® 10 DX Block Diagram
1.4. Intel® Stratix® 10 DX Family Plan
1.5. Intel® Hyperflex™ Core Architecture
1.6. Heterogeneous 3D SiP Transceiver Tiles
1.7. Intel® Stratix® 10 DX Transceivers
1.8. Heterogeneous 3D Stacked HBM2 DRAM Memory
1.9. External Memory and General Purpose I/O
1.10. Adaptive Logic Module (ALM)
1.11. Core Clocking
1.12. I/O PLLs
1.13. Internal Embedded Memory
1.14. Variable Precision DSP Block
1.15. Hard Processor System (HPS)
1.16. Power Management
1.17. Device Configuration and Secure Device Manager (SDM)
1.18. Device Security
1.19. Configuration via Protocol Using PCI Express*
1.20. Partial and Dynamic Reconfiguration
1.21. Fast Forward Compile
1.22. Single Event Upset (SEU) Error Detection and Correction
1.23. Document Revision History for the Intel® Stratix® 10 DX Device Overview
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1.12. I/O PLLs
Intel® Stratix® 10 DX devices contain up to 24 integer I/O PLLs (IOPLLs) available for general purpose use in the core fabric and for simplifying the design of external memory interfaces and high-speed LVDS interfaces. The IOPLLs are located in each bank of 48 general purpose I/O, one per I/O bank, adjacent to the hard memory controllers and LVDS SerDes in each I/O bank. This makes it easier to close timing because the IOPLLs are tightly coupled with I/Os that need to use them. The IOPLLs can be used for general purpose applications in the core such as clock network delay compensation and zero-delay clock buffering