Stratix® 10 DX Device Overview

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ID 683225
Date 9/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 DX Device Overview
1. Intel® Stratix® 10 DX Device Overview x
1.1. Intel® Stratix® 10 DX Devices 1.2. Intel® Stratix® 10 DX Features Summary 1.3. Intel® Stratix® 10 DX Block Diagram 1.4. Intel® Stratix® 10 DX Family Plan 1.5. Intel® Hyperflex™ Core Architecture 1.6. Heterogeneous 3D SiP Transceiver Tiles 1.7. Intel® Stratix® 10 DX Transceivers 1.8. Heterogeneous 3D Stacked HBM2 DRAM Memory 1.9. External Memory and General Purpose I/O 1.10. Adaptive Logic Module (ALM) 1.11. Core Clocking 1.12. I/O PLLs 1.13. Internal Embedded Memory 1.14. Variable Precision DSP Block 1.15. Hard Processor System (HPS) 1.16. Power Management 1.17. Device Configuration and Secure Device Manager (SDM) 1.18. Device Security 1.19. Configuration via Protocol Using PCI Express* 1.20. Partial and Dynamic Reconfiguration 1.21. Fast Forward Compile 1.22. Single Event Upset (SEU) Error Detection and Correction 1.23. Document Revision History for the Intel® Stratix® 10 DX Device Overview
1.4. Intel® Stratix® 10 DX Family Plan x
1.4.1. Available Options
1.7. Intel® Stratix® 10 DX Transceivers x
1.7.1. Intel® P-Tile Transceivers and Hard IP 1.7.2. Intel® E-Tile Transceivers and Hard IP
1.15. Hard Processor System (HPS) x
1.15.1. Key Features of the Intel® Stratix® 10 HPS
1. Intel® Stratix® 10 DX Device Overview

1.4. Intel® Stratix® 10 DX Family Plan

Table 2.   Intel® Stratix® 10 DX FPGA Family Plan—FPGA Core (part 1)

Intel® Stratix® 10 DX

Device Name

 Logic Elements (KLE) eSRAM Blocks eSRAM Mbits M20K Blocks M20K Mbits MLAB Counts MLAB Mbits
DX 1100 1,325 — — 5,461 107 11,556 7
DX 2100 2,073 2 94.5 6,847 134 17,856 11
DX 2800 2,753 — — 11,721 229 23,796 15

Table 3.   Intel® Stratix® 10 DX FPGA Family Plan—DSP, HPS, Interconnects, and PLLs (part 2)

Intel® Stratix® 10 DX

Device Name

18x19

Multipliers1

HPS Quad Core Interconnects PLL

Maximum

GPIOs

Maximum

Transceiver

External

Memory

Interfaces

(x72 width)

 I/O PLLs
DX 1100 5,184 Yes 528 32 2 16
DX 2100 7,920 — 612 84 4 16
DX 2800 11,520 — 816 84 4 24

Table 4.   Intel® Stratix® 10 DX FPGA Family Plan—Hard IP and HBM2 (part 3)

Intel® Stratix® 10 DX

Device Name

 Hard IP HBM2 Tile Layout
Config PCIe* Gen4x16, or Intel® UPI, Hard IP Blocks PCIe* Gen4x16 Only, Hard IP Blocks 10/25/100 GbE MACs Bandwidth (GBps) Density (GB)
DX 1100 — 1 4 — — Figure 2
DX 2100 3 — 4 512 8 Figure 3
DX 2800 3 1 2 — — Figure 4

Table 5.   Intel® Stratix® 10 DX FPGA Package PlanCell legend: General Purpose I/Os, High-voltage I/Os, LVDS Pairs, P-tile Transceivers, E-tile Transceivers. 2 3 4 5

Intel® Stratix® 10 DX

Device Name

F1760

JF43- 32 Transceivers

(42.5 mm x 42.5 mm)

F2597

TF53- 84 Transceivers

(52.5 mm x 52.5 mm)

F2912

TF55- 84 Transceivers

(55 mm x 55 mm)
DX 1100 528, 0, 264, 16, 16 — —
DX 2100 — 612, 0, 306, 60, 24 —
DX 2800 — — 816, 0, 408, 76, 8
Figure 2.  Intel® Stratix® 10 DX 1100, 1 P-Tile, 1 E-Tile (32 Transceiver Channels)
Note: The P-tile with 16 channels can be used for PCIe* only, not for Intel® UPI.
Figure 3.  Intel® Stratix® 10 DX 2100, 3 P-Tiles, 1 E-Tile (84 Transceiver Channels) and 2 HBM2 (8 GBytes total)
Note: The P-tile with 20 channels can be used for either PCIe* , or for Intel® UPI.
Figure 4.  Intel® Stratix® 10 DX 2800, 4 P-Tiles, 1 E-Tile (84 Transceiver Channels)
Note:

The P-tile with 16 channels can be used for PCIe* only, not for Intel® UPI.

The P-tile with 20 channels can be used for either PCIe* , or for Intel® UPI.


Section Content
Available Options

1 The number of 27x27 multipliers is one-half the number of 18x19 multipliers.
2 All packages are ball grid arrays with 1.0 mm pitch.
3 High-voltage I/O pins are used for 3 V and 2.5 V interfacing.
4 Each LVDS pair can be configured as either a differential input or a differential output.
5 High-voltage I/O pins and LVDS pairs are included in the General Purpose I/O count. Transceivers are counted separately.
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