Stratix® 10 DX Device Overview

ID 683225
Date 9/07/2023

1.8. Heterogeneous 3D Stacked HBM2 DRAM Memory

Select Intel® Stratix® 10 DX devices integrate 3D stacked High-Bandwidth DRAM Memory (HBM2) alongside a high-performance monolithic 14 nm FPGA fabric die, and multiple high-speed transceiver tiles, all inside a single flip-chip FBGA package.

This results in a “near memory” implementation where the high-density stacked DRAM is integrated very close to the FPGA in the same package. In this configuration the in-package memory is able to deliver up to 512 GBps of total aggregate bandwidth which represents over a 10X increase in bandwidth compared to traditional “far memory” implemented in separate devices on the board. A near memory configuration also reduces system power by reducing traces between the FPGA and memory, while also reducing board area.

Figure 8. Heterogeneous 3D Stacked HBM2 DRAM Architecture

Select Intel® Stratix® 10 DX devices integrate two 3D HBM2 DRAM memory stacks inside the package. Each of these DRAM stacks has:

  • 4 GB density per stack, for a total density of 8 GB per device
  • 256 GBps bandwidth per stack, for a total aggregate bandwidth of 512 GBps per device
  • 8 independent channels, each 128 bits wide, or 16 independent pseudo channels, each 64 bits wide (in pseudo channel mode)
  • Data transfer rates up to 2 Gbps, per signal, between core fabric and HBM2 DRAM
  • Half-rate transfer to core fabric

Intel® Stratix® 10 DX devices use embedded hard memory controllers to access the HBM2 DRAM.