Stratix® 10 DX Device Overview

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ID 683225
Date 9/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 DX Device Overview
1. Intel® Stratix® 10 DX Device Overview x
1.1. Intel® Stratix® 10 DX Devices 1.2. Intel® Stratix® 10 DX Features Summary 1.3. Intel® Stratix® 10 DX Block Diagram 1.4. Intel® Stratix® 10 DX Family Plan 1.5. Intel® Hyperflex™ Core Architecture 1.6. Heterogeneous 3D SiP Transceiver Tiles 1.7. Intel® Stratix® 10 DX Transceivers 1.8. Heterogeneous 3D Stacked HBM2 DRAM Memory 1.9. External Memory and General Purpose I/O 1.10. Adaptive Logic Module (ALM) 1.11. Core Clocking 1.12. I/O PLLs 1.13. Internal Embedded Memory 1.14. Variable Precision DSP Block 1.15. Hard Processor System (HPS) 1.16. Power Management 1.17. Device Configuration and Secure Device Manager (SDM) 1.18. Device Security 1.19. Configuration via Protocol Using PCI Express* 1.20. Partial and Dynamic Reconfiguration 1.21. Fast Forward Compile 1.22. Single Event Upset (SEU) Error Detection and Correction 1.23. Document Revision History for the Intel® Stratix® 10 DX Device Overview
1.4. Intel® Stratix® 10 DX Family Plan x
1.4.1. Available Options
1.7. Intel® Stratix® 10 DX Transceivers x
1.7.1. Intel® P-Tile Transceivers and Hard IP 1.7.2. Intel® E-Tile Transceivers and Hard IP
1.15. Hard Processor System (HPS) x
1.15.1. Key Features of the Intel® Stratix® 10 HPS
1. Intel® Stratix® 10 DX Device Overview

1.8. Heterogeneous 3D Stacked HBM2 DRAM Memory

Select Intel® Stratix® 10 DX devices integrate 3D stacked High-Bandwidth DRAM Memory (HBM2) alongside a high-performance monolithic 14 nm FPGA fabric die, and multiple high-speed transceiver tiles, all inside a single flip-chip FBGA package.

This results in a “near memory” implementation where the high-density stacked DRAM is integrated very close to the FPGA in the same package. In this configuration the in-package memory is able to deliver up to 512 GBps of total aggregate bandwidth which represents over a 10X increase in bandwidth compared to traditional “far memory” implemented in separate devices on the board. A near memory configuration also reduces system power by reducing traces between the FPGA and memory, while also reducing board area.

Figure 8. Heterogeneous 3D Stacked HBM2 DRAM Architecture

Select Intel® Stratix® 10 DX devices integrate two 3D HBM2 DRAM memory stacks inside the package. Each of these DRAM stacks has:

  • 4 GB density per stack, for a total density of 8 GB per device
  • 256 GBps bandwidth per stack, for a total aggregate bandwidth of 512 GBps per device
  • 8 independent channels, each 128 bits wide, or 16 independent pseudo channels, each 64 bits wide (in pseudo channel mode)
  • Data transfer rates up to 2 Gbps, per signal, between core fabric and HBM2 DRAM
  • Half-rate transfer to core fabric

Intel® Stratix® 10 DX devices use embedded hard memory controllers to access the HBM2 DRAM.

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