Intel® Stratix® 10 DX Device Overview

ID 683225
Date 9/28/2020
Public

1. Intel® Stratix® 10 DX Device Overview

Targeting high-performance acceleration applications, increasingly used in Datacenter, Networking, Cloud Computing, and Test & Measurement markets, Intel® Stratix® 10 DX FPGAs feature hard intellectual property blocks supporting both coherent and non-coherent protocol interfaces.

A low latency, high performance coherent interface is achieved when connecting the FPGA to selected Intel® Xeon® Scalable Processors via Intel® Ultra Path Interconnect (UPI), while the non-coherent interface takes advantage of any PCI Express* (PCIe) Gen4 capable device.

The FPGA's external memory capability now includes support for a new DDR-T soft IP memory controller, allowing interfaces to attach up to 1 TB of high-performance, persistent Intel® Optane™ PMem modules per controller, directly to the FPGAs GPIO banks.

In addition to supporting these interface protocols, the DX variant FPGAs also offer hard intellectual property blocks for 100 Gigabit Ethernet and DDR4 memory control, combined with a high-performance monolithic 14 nm FPGA fabric die, all inside a single flip-chip FBGA package. Select Intel® Stratix® 10 DX devices include an integrated quad-core 64-bit Arm* Cortex* -A53 hard processor subsystem (HPS) on the fabric die, or embedded 3D stacked High-Bandwidth (up to 512 GB/s) DRAM memory (HBM2) inside the package.

As part of the Intel® Stratix® 10 family, the DX variant devices feature other innovations such as the Intel® Hyperflex™ core architecture, variable precision DSP blocks with hardened support for both floating-point and fixed-point operation, and advanced packaging technology based on Intel® Embedded Multi-die Interconnect Bridge (EMIB).

Important innovations in Intel® Stratix® 10 DX devices include:

  • Intel® Hyperflex™ core architecture delivering higher core performance compared to previous generation high-performance FPGAs
  • Manufactured using Intel® high volume 14 nm tri-gate (FinFET) technology
  • Intel® Embedded Multi-die Interconnect Bridge (EMIB) packaging technology
  • A soft IP memory controller and PHY supporting DDR-T to directly attach Intel® Optane™ PMem modules to the FPGA, two to four controllers per FPGA, and rates up to 2400 megatransfers per second (one module per channel)
  • Transceivers on separate heterogeneous tiles, supporting data rates up to 57.8 gigabits per second (Gbps) Pulse Amplitude Modulation (PAM4) and 28.9 Gbps non-return-to-zero (NRZ) for chip-to-chip, chip-to-module, and backplane driving
  • Hard PCI Express* Gen4 x16 intellectual property blocks, with useful features such as endpoint and root port modes, multiple independent controllers, virtualization support for single-root I/O virtualization (SR-IOV), virtual I/O device (VIRTIO), Intel® Scalable I/O Virtualization ( Intel® Scalable IOV), and transaction layer bypass mode
  • Hard Intel® UPI intellectual property blocks in select devices, supporting Home Agent soft IP
  • Hard 100G Ethernet MAC, 100G Reed-Solomon forward error correction (FEC), and KP-FEC blocks
  • 3D stacked High-Bandwidth DRAM Memory (HBM2) in select devices
  • Monolithic core fabric with up to 2.8 million logic elements (LEs)
  • Hard fixed-point and IEEE 754 compliant hard floating-point variable precision digital signal processing (DSP) blocks
  • Hard memory controllers and PHY supporting DDR4 rates up to 2666 megabits per second (Mbps) per pin
  • Hard HBM2 memory controllers in devices that include in-package 3D stacked HBM2 DRAM memory
  • M20K, 20 kilobit (Kb) internal SRAM memory blocks
  • eSRAM, 47.25 megabit (Mb) internal SRAM blocks in select devices
  • Quad-core 64-bit Arm* Cortex* -A53 embedded processor running up to 1.5 GHz in select devices, processor subsystem peripherals, and high bandwidth buses to and from the FPGA logic fabric
  • Programmable clock tree synthesis for flexible, low power, low skew clock trees
  • Dedicated Secure Device Manager (SDM) for enhanced device configuration and security, supporting AES-256, SHA-256/384 and elliptic curve digital signature algorithm (ECDSA) -256/384 encrypt/decrypt accelerators, and multi-factor authentication
  • Comprehensive set of advanced power saving features

Did you find the information on this page useful?

Characters remaining:

Feedback Message