Stratix® 10 DX Device Overview

ID 683225
Date 9/07/2023

1.1. Intel® Stratix® 10 DX Devices

In addition to the coherent and non-coherent protocol interfaces that are required for high-performance acceleration applications, Intel® Stratix® 10 DX FPGAs deliver improved core logic performance compared to previous generation high-performance FPGAs, with densities up to 2.8 million LEs in a monolithic fabric.

The devices also feature up to 84 full-duplex transceivers on separate transceiver tiles, a subset of which are capable of supporting data rates up to 57.8 Gbps PAM4 and 28.9 Gbps NRZ for both short reach and backplane driving applications. External memory interfaces up to 2666 Mbps DDR4 are achieved using hard memory controllers, and some DX variant devices include in-package 3D stacked HBM2 DRAM memory capable of supporting 512 gigabytes per second (GBps) memory bandwidth. Select devices contain an embedded hard processor system (HPS) based on an application-class quad-core 64-bit Arm* Cortex* -A53, running at clock rates up to 1.5 GHz, including processor peripherals and high-bandwidth buses to and from the FPGA logic fabric.

The high-performance monolithic FPGA fabric is based on the Intel® Hyperflex™ core architecture that includes additional Hyper-Registers everywhere throughout the interconnect routing and at the inputs of all functional blocks. The core fabric also contains an enhanced logic array utilizing Intel’s adaptive logic module (ALM) and a rich set of high-performance building blocks including:

  • M20K, 20 Kb embedded SRAM memory blocks
  • eSRAM, 47.25 Mb embedded SRAM memory blocks (in select devices)
  • Variable precision DSP blocks with hard fixed point and IEEE 754 compliant hard floating-point
  • General purpose IO cells with integer PLLs in every IO bank
  • Hard memory controllers and PHY for external memory interfaces
  • Hard memory controllers for in-package 3D stacked HBM2 DRAM memory (in select devices)

To clock these fabric building blocks, Intel® Stratix® 10 DX FPGAs use programmable clock tree synthesis, which uses dedicated clock tree routing to synthesize only those branches of the clock trees required for the application.

The high-speed serial transceivers contain both the physical medium attachment (PMA) and the physical coding sublayer (PCS) required to implement a variety of industry standard protocols. In addition to the hard PCS for each transceiver, Intel® Stratix® 10 DX devices contain hard PCI Express* IP that supports up to Gen4 x16 lane configuration, hard Intel® UPI IP in select devices that supports Home Agent soft IP, and hard 10/25/100 Gbps Ethernet MAC IP with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514). These hardened intellectual property blocks free up valuable core logic resources, save power, and increase your productivity.

All Intel® Stratix® 10 DX devices support in-system, fine-grained partial reconfiguration of the logic array, allowing logic add and subtract from the system while it is operating.