Visible to Intel only — GUID: joc1433527111814
Ixiasoft
1.1. Intel® Stratix® 10 DX Devices
1.2. Intel® Stratix® 10 DX Features Summary
1.3. Intel® Stratix® 10 DX Block Diagram
1.4. Intel® Stratix® 10 DX Family Plan
1.5. Intel® Hyperflex™ Core Architecture
1.6. Heterogeneous 3D SiP Transceiver Tiles
1.7. Intel® Stratix® 10 DX Transceivers
1.8. Heterogeneous 3D Stacked HBM2 DRAM Memory
1.9. External Memory and General Purpose I/O
1.10. Adaptive Logic Module (ALM)
1.11. Core Clocking
1.12. I/O PLLs
1.13. Internal Embedded Memory
1.14. Variable Precision DSP Block
1.15. Hard Processor System (HPS)
1.16. Power Management
1.17. Device Configuration and Secure Device Manager (SDM)
1.18. Device Security
1.19. Configuration via Protocol Using PCI Express*
1.20. Partial and Dynamic Reconfiguration
1.21. Fast Forward Compile
1.22. Single Event Upset (SEU) Error Detection and Correction
1.23. Document Revision History for the Intel® Stratix® 10 DX Device Overview
Visible to Intel only — GUID: joc1433527111814
Ixiasoft
1.21. Fast Forward Compile
The innovative Fast Forward Compile feature in the Intel® Quartus® Prime software identifies performance bottlenecks in your design and provides detailed, step-by-step performance improvement recommendations that you can then implement. The Compiler reports estimates of the maximum operating frequency that can be achieved by applying the recommendations. As part of the new Hyper-Aware design flow, Fast Forward Compile maximizes the performance of your Intel® Stratix® 10 DX design and achieves rapid timing closure.
Previously, this type of optimization required multiple time-consuming design iterations, including full design re-compilation to determine the effectiveness of the changes. Fast Forward Compile enables you to make better decisions about where to focus your optimization efforts, and how to increase your design performance and throughput. This technique removes much of the guesswork of performance exploration, resulting in fewer design iterations.