Stratix® 10 DX Device Overview

ID 683225
Date 9/07/2023

1.7.1. Intel® P-Tile Transceivers and Hard IP

Intel® Stratix® 10 DX devices contain one or more P-tiles, each P-tile containing up to 20 full-duplex transceiver channels, along with PCIe* Gen4 x16 hard IP and Intel® UPI hard IP. If all 20 channels from the P-tile are available in the device, the P-tile can be configured to support either a PCIe* interface or an Intel® UPI interface. If only 16 channels are available, the P-tile supports PCIe* but does not support Intel® UPI which requires all 20 channels. Support for protocols other than PCIe* or Intel® UPI is not possible with the P-tile; it is not possible to bypass the hard IP blocks and connect the P-tile transceivers directly to the FPGA fabric.

Table 6.   Intel® Stratix® 10 P-Tile PCIe* Features



PCIe* Configurations

  • Gen4 or Gen3, x16 endpoint or root port
  • Gen4 or Gen3, x8 + x8 static port bifurcation, endpoints only
  • Gen4 or Gen3, x4 + x4 + x4 + x4 static port bifurcation, root ports only
  • Gen2 and Gen1 configurations supported indirectly through link negotiation
  • x1, x2 widths supported indirectly through protocol width reduction capability
  • Chip-to-chip and low-loss cable support

Virtualization Support

  • Single-Root I/O Virtualization (SR-IOV), 8 physical functions (PF) and 2048 virtual functions (VF) per endpoint
  • Intel® Scalable IOV support for software-based virtualization
  • Virtual I/O Device (VIRTIO)

Switch Support

  • Transaction Layer Bypass (TLP bypass) enables PCIe* switch implementations using SWUP and SWDN ports
Table 7.   Intel® Stratix® 10 P-Tile Intel® UPI Features



Intel® UPI Configurations

  • 20 lane support for 9.6 GT/s, 10.4 GT/s, 11.2 GT/s data rates
  • PHY and Link Layer support for Home Agent soft IP, Home Agent is implemented in the FPGA fabric
  • Chip-to-chip and low-loss cable support