3.7.2. Toolkit GUI Settings
- The MAC and PHY tab implements various control and status registers (CSR) for both the hardened custom PCS core and the MAC soft logic.
- The Traffic Statistics and Bandwidth Performance tab implements various Control and Status Registers (CSR) for the Demo Management module to configure the traffic generator and checker. Additionally, it also provides a real-time bandwidth calculation measurement result based on the traffic modules instantiated in the example design.
- The Help tab provides useful next-step troubleshooting information based on the assertion and deassertion of specific status registers or output ports if any errors happen after the link initialization is executed.
The MAC and PHY tab shows a step-by-step guide for link initialization and real-time status monitoring of a Serial Lite IV IP link.
The toolkit continuously reads and displays all of the essential status registers related to the Serial Lite IV IP link after you execute the following stages:
- Click Assert Full System Reset to perform a full system reset.
- Click Link Initialization to perform link initialization with internal/external loopback enabled..
- Click Read PCS Status to poll all corresponding status registers and output ports from both hardened custom PCS and MAC soft logic.
- Click Read FEC Statistics to generate the FEC statistics report after steps 1–3 complete successfully and the link is up and running.
In case of any failure, the toolkit narrows down to the type of failure based on the various status bits, which are based on the register bank or output port from the hardened custom PCS core or MAC soft logic. The corresponding next-step debugging information is displayed in the Help tab.
The Help tab provides useful next-step debugging information based on the errors or status registers reported from the MAC and PCS status in the MAC and PHY tab.
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