Serial Lite IV Intel® Stratix™ 10 FPGA IP Design Example User Guide

ID 683223
Date 11/01/2021
Document Table of Contents

3.1. Features

You can use the design example to test the following features of the Serial Lite IV IP:
  • Basic and full transmission modes:
    • Basic mode—This is a pure streaming mode where data is sent without the start-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IP takes the first valid data as the start of a burst.
    • Full mode—This is a packet transfer mode. This mode sends a burst and a sync cycle at the start and end of a packet as delimiters.
  • Master and slave test mode in hardware testing.
  • Transceiver data rate up to:
    • 56 Gbps per lane with a maximum of eight PAM4 lanes in a single link with RS-FEC feature 2
    • 28 Gbps per lane with a maximum of 16 NRZ lanes with optional RS-FEC feature2.
  • Data error reporting including PCS errors, loss of alignment, CRC errors, and data invalid errors on the RX datapath.
  • Traffic checker for data verification and lane deskew verification.
  • System console commands for hardware testing.
  • Serial Lite IV IP debugging toolkit.
  • Debugging sequence.
2 The maximum data rate that the IP can achieve depends on the device speed grade. Refer to Intel® Stratix® 10 Device Data Sheet for more information about maximum data rate for each device speed grade.