1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for Serial Lite IV Design Example 4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
You can use the design example to test the following features of the Serial Lite IV IP:
- Basic and full transmission modes:
- Basic mode—This is a pure streaming mode where data is sent without the start-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IP takes the first valid data as the start of a burst.
- Full mode—This is a packet transfer mode. This mode sends a burst and a sync cycle at the start and end of a packet as delimiters.
- Master and slave test mode in hardware testing.
- Transceiver data rate up to:
- Data error reporting including PCS errors, loss of alignment, CRC errors, and data invalid errors on the RX datapath.
- Traffic checker for data verification and lane deskew verification.
- System console commands for hardware testing.
- Serial Lite IV IP debugging toolkit.
- Debugging sequence.
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