Serial Lite IV Intel® Stratix™ 10 FPGA IP Design Example User Guide

ID 683223
Date 11/01/2021
Public
Document Table of Contents

3.2.6. Demo Control

The design example uses the demo control module to configure the transceiver and the demo management module. It has separate Avalon® memory-mapped interfaces connected to the transceiver reconfiguration block and the demo management module. The demo control module also has a JTAG master, parallel input/output (PIO) interface, and an In-system Source and Probe (ISSP) modules for debugging through system console.

This modules is only available in the hardware design example.

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