Serial Lite IV Intel® Stratix™ 10 FPGA IP Design Example User Guide

ID 683223
Date 11/01/2021
Public
Document Table of Contents

3.2.5. Demo Management

The demo management module implements control and status registers to control and monitor the design example operation. This module monitors and logs errors that occur during the design example operation.

This modules is only available in the hardware design example.

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