3.4. Hardware Testing
The hardware design example provides two test methods; the loopback test mode and the master and slave test mode. For loopback test mode, the traffic generator sends packets to the Serial Lite IV TX core and loopback to the RX core either internally or externally. For the master and slave test mode, you need to set up two separate development kits; a master development kit to generate and verify packets and a slave development kit to receive and transfer packets back to the master.
You can test the design example using the system console.
To use the system console script, navigate to the ./ed_hwtest/system_console directory. Source the sliv_etile.tcl script. The system console script provides useful commands for reading statistics and enables you to control various features in the design.
|list_jtag||Displays a list of JTAG master indexes that are connected to your board.|
|set_jtag <jtag master_index number>||Selects the JTAG master.
Note: After programming the .sof file, perform either sl4_link_init_int_lpbk or sl4_link_init_ext_lpbk before running the design example for proper transceiver calibration.
|sl4_link_init_int_lpbk||Enables TX to RX internal serial loopback within the transceiver and performs the specific transceiver calibration flow.|
|sl4_link_init_ext_lpbk||Enables TX to RX external loopback and performs the specific transceiver calibration flow.|
|traffic_gen_enable||Enables the traffic generator and checker.
The hardware design example runs in basic or pure streaming mode by default when the traffic generator is enabled.
|traffic_gen_disable||Disables the traffic generator and checker.|
|tx_source_traffic_reset||Resets the TX datapath for the DCFIFO and traffic generator.|
|rx_sink_traffic_reset||Resets the RX datapath for the DCFIFO and traffic checker.|
|read_error_statistic||Displays the error statistics.|
|continuous_mode_en||Resets the TX and RX core (MAC and PHY) and enables the traffic generator to generate continuous (single continuous data generation) traffic stream.|
|burst_mode_en||Resets the TX and RX core (MAC and PHY) and enables the traffic generator to generate a burst (multiple burst packet data generation) traffic stream.|
|crc_err_inject_pulse||Enables CRC error injection for all lanes.|
|slave_test_mode_enable||This option disables the traffic generator/checker and enables the traffic to flow from sink to source. This option is only available for hardware setup with master and slave configuration using two different development kits.|
|slave_test_mode_disable||This option disables data flow from sink to source. Select option 1 to enable the data generator and data checker.|
In addition to this command script, you can also use the Serial Lite IV IP toolkit for real-time troubleshooting during active link operation.
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