Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

Download PDF
ID 683193
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.3.12.1. Upstream Requests

Table 30.  Protocol Flow for Upstream Request from AFU to FIUThe Tx Data column identifies whether the request expects a Tx Data payload. The Rx Data column identifies whether the response returns an Rx Data payload.
Type Tx Request Tx Data Rx Response Rx Data
Memory Write WrLine_I Yes WrLine No
WrLine_M
WrPush_I
Memory Read RdLine_I No RdLine Yes
RdLine_S
Special Messages WrFence No WrFence No
Interrupt No Interrupt No
Table 31.  Protocol Flow for Upstream Request from AFU to FIU
  • WrLine_I: Requires special handling, because it must first write to the CL and then evict it from the cache. The eviction forms Phase 2 of the request.
  • RdLine_I: Recommended as the default read type.
  • RdLine_S: Use sparingly only for cases where you have identified highly referenced CLs.
  • RdCode: Updates the CPU directory and lets the FPGA cache the line in Shared state. RdCur does NOT update the CPU directory, FPGA does not cache this line. A future access to this line from CPU, does not snoop the FPGA.
CCI-P Request FPGA Cache UPI Cycle Next State CCI-P Response UPI Cycle Next State CCI-P Response UPI Cycle Next State
Hit/Miss State Phase 1 Phase 2 Phase 3
WrLine_I Hit M None M WrLine WbMtoI I      
Hit S InvItoE    
Miss I    
WrLine_M Hit M None M WrLine NA        
Hit S InvtoE    
Miss I    
WrLine_I Miss M WbMotI I   InvItoE M WrLine WbMotI I
WrLine_M    
WrPush_I WbPushMotI I
WrLine_I Miss S EvctCln I   InvItoE M WrLine WbMotI I
WrLine_M    
WrPush_I WbPushMotI I
WrPush_I Hit M None M WrLine WbPushMotI I      
S,I InvItoE    
RdLine_S Hit S,M None No Change RdLine N.A        
Miss I RdCode S RdLine      
RdLine_I Hit S,M None No Change RdLine NA        
Miss I RdCur I RdLine      
RdLine_I Miss M WbMtoI I   RdCur I RdLine    
RdLine_S RdCode S    
RdLine_I S EvctCln RdCur I    
RdLine_S RdCode S    
Level Two Title