Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

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ID 683193
Date 11/04/2019
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Document Table of Contents
Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

Document Version Intel Acceleration Stack Version Changes
2019.11.04 2.0.1 (supported with Intel® Quartus® Prime Pro Edition 19.2)and 2.0 (supported with Intel® Quartus® Prime Pro Edition 18.1.2) and 1.2 (supported with Intel® Quartus® Prime Pro Edition 17.1.1) Added the feature CCI-P Byte Enable.
2019.08.05 2.0 (supported with Intel® Quartus® Prime Pro Edition 18.1.2) and 1.2 (supported with Intel® Quartus® Prime Pro Edition 17.1.1)
  • Acronym List for Acceleration Stack for CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual: Added Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) to the RdLine_I acronym.
  • Memory and Cache Hierarchy: Updated the Intel FPGA PAC Memory Hierarchy figure.
  • CCI-P Interface: Updated the CCI-P Signals figure.
  • MMIO Requests: Changed 64-byte to 64-bit in this sentence: "The FIU maps the AFU's MMIO address space to a 64-bit prefetchable PCIe* BAR."
2018.12.04 1.2 (supported with Intel® Quartus® Prime Pro Edition 17.1.1) Added the " Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual Archives" section that contains the archived versions of this document.
2018.08.06 1.1 (supported with Intel® Quartus® Prime Pro Edition 17.1.1) and 1.0 (supported with Intel® Quartus® Prime Pro Edition 17.0.0) Removed detailed clock frequencies from Table 6 in the "Comparison of FIU Capabilities" section; and removed the "Clock Frequency" section from the document.
Note: Removed clock frequencies from document because there are multiple platforms discussed in this document.
2018.04.11 1.0 (supported with Intel® Quartus® Prime Pro Edition 17.0)
  • Document restructured to explicitly define the differences between the Intel® FPGA PAC and the Integrated FPGA Platform.
  • Added IRQ ordering with respect to writes, reads, and write fences added to the "Memory Requests" section.
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