1.2.1. FPGA Interface Manager (FIM)
- EMIF for interfacing to external memory
- HSSI for external transceiver interfacing
For more information, refer to your platform for specific details about the FIM implementation.
The FIU acts like a bridge between the AFU and the platform. Figure 1 shows the FIU connection between the PCIe, SMBus for manageability, and the full UPI stack to the host. In addition, the FIM also owns all hard IPs on FPGA (for example PLLs), partial reconfiguration (PR) engine, JTAG atom, IOs, and temperature sensors. The FIM is configured first at boot up and persists until the platform power cycles, whereas the AFU can be dynamically reconfigured. Intel partial reconfiguration technology enables the dynamic reconfiguration capability, where the AFU is defined as a partial reconfiguration region and the FIM is defined as a static region. The interfaces between AFU and FIU provides hot plug capability to pause the traffic, and to re-enumerate the AFU after partial reconfiguration.
The FIM may present one or more interfaces to the AFU, depending on the platform capabilities. This document focuses on CCI-P, an interface for the AFU to communicate with the Intel® Xeon® processor. The CCI-P provides address space isolation and protection using Intel Virtual Technology for Directed I/O (Intel VT-d). The CCI-P has the same protections that are defined for a PCIe function. An AFU is a single function device from a PCIe enumeration and VT-d point of view.The FIU may also implement manageability functions like error monitoring and reporting, power and temperature monitoring, configuration bootstrap, bitstream security flows, and remote debug to ease the deployment and management of FPGAs in a data center environment. In some implementations, FIU may also have an out-of-band communication interface to the board management controller (BMC).
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