Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
                    
                        ID
                        683193
                    
                
                
                    Date
                    11/04/2019
                
                
                    Public
                
            
                                    
                                    
                                        
                                        
                                            1.3.1. Signaling Information
                                        
                                        
                                    
                                        
                                            1.3.2. Read and Write to Main Memory
                                        
                                        
                                        
                                    
                                        
                                        
                                            1.3.3. Interrupts
                                        
                                        
                                    
                                        
                                        
                                            1.3.4. UMsg
                                        
                                        
                                    
                                        
                                        
                                            1.3.5. MMIO Accesses to I/O Memory
                                        
                                        
                                    
                                        
                                        
                                            1.3.6. CCI-P Tx Signals
                                        
                                        
                                    
                                        
                                        
                                            1.3.7. Tx Header Format
                                        
                                        
                                    
                                        
                                            1.3.8. CCI-P Rx Signals
                                        
                                        
                                        
                                    
                                        
                                        
                                            1.3.9. Multi-Cache Line Memory Requests
                                        
                                        
                                    
                                        
                                            1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005)
                                        
                                        
                                        
                                    
                                        
                                        
                                            1.3.11. Additional Control Signals
                                        
                                        
                                    
                                        
                                            1.3.12. Protocol Flow
                                        
                                        
                                        
                                    
                                        
                                            1.3.13. Ordering Rules
                                        
                                        
                                        
                                    
                                        
                                        
                                            1.3.14. Timing Diagram
                                        
                                        
                                    
                                        
                                        
                                            1.3.15. CCI-P Guidance
                                        
                                        
                                    
                                
                            1.5. Intel® FPGA Basic Building Blocks
Intel® FPGA Basic Building Blocks (BBBs) are Intel-provided IPs that users can instantiate in their AFU. There are two types of BBBs: software-visible (exposes a register interface and requires software interaction) and software-invisible (does not require software interaction). In both cases, if you are the AFU developer, it is your responsibility to integrate the hardware and software into your AFU.
For more information about BBBs, refer to the " Intel® FPGA Basic Building Blocks (BBB)" web page.
   Related Information