Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
                    
                        ID
                        683193
                    
                
                
                    Date
                    11/04/2019
                
                
                    Public
                
            
                                    
                                    
                                        
                                        
                                            1.3.1. Signaling Information
                                        
                                        
                                    
                                        
                                            1.3.2. Read and Write to Main Memory
                                        
                                        
                                        
                                    
                                        
                                        
                                            1.3.3. Interrupts
                                        
                                        
                                    
                                        
                                        
                                            1.3.4. UMsg
                                        
                                        
                                    
                                        
                                        
                                            1.3.5. MMIO Accesses to I/O Memory
                                        
                                        
                                    
                                        
                                        
                                            1.3.6. CCI-P Tx Signals
                                        
                                        
                                    
                                        
                                        
                                            1.3.7. Tx Header Format
                                        
                                        
                                    
                                        
                                            1.3.8. CCI-P Rx Signals
                                        
                                        
                                        
                                    
                                        
                                        
                                            1.3.9. Multi-Cache Line Memory Requests
                                        
                                        
                                    
                                        
                                            1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005)
                                        
                                        
                                        
                                    
                                        
                                        
                                            1.3.11. Additional Control Signals
                                        
                                        
                                    
                                        
                                            1.3.12. Protocol Flow
                                        
                                        
                                        
                                    
                                        
                                            1.3.13. Ordering Rules
                                        
                                        
                                        
                                    
                                        
                                        
                                            1.3.14. Timing Diagram
                                        
                                        
                                    
                                        
                                        
                                            1.3.15. CCI-P Guidance
                                        
                                        
                                    
                                
                            1.3.2.2. Writing to Main Memory
The AFU sends memory write requests over CCI-P Channel 1 (C1), using pck_af2cp_sTx.c1; and receives write completion acknowledgement responses over C1, using pck_cp2af_sRx.c1.
    The c1_ReqMemHdr structure provides a convenient mapping from flat bit-vector to write request fields. The AFU asserts pck_af2cp_sTx.c1.valid signal and drives the memory write request and data on hdr and data, respectively. The req_type signal specifies the request type and caching hint: 
    
 
   - WrLine_I to specify no FPGA caching intent
- WrLine_M to specify intent to leave FPGA cache in M state
- WrPush_I for intent to cache in processor-side cache
    The c1_ReqMemHdr structure also provides a mode field pck_af2cp_sTx.c1.hdr.mode that specifies which type of memory write request to issue. The two memory write request modes are as follows: 
    
 
   - eMOD_CL to specify a single or multi cache-aligned write
-  eMOD_BYTE to specify a byte enable write 
      Note: This memory request mode is not available for Intel® PAC with Intel® Arria® 10 GX FPGA.
The c1_RspMemHdr structure provides a convenient mapping from flat bit-vector to response fields. FIU asserts pck_cp2af_sRx.c1.resp_valid signal and drives the read response on hdr. The resp_type field is decoded to decode the response type: Memory write, Write Fence or Interrupt.
A WrFence is used to make the memory write requests globally visible. WrFence request follows the same flow as memory write requests, except that it does not accept a data payload and address.
For more information, refer to the Write Request header format in the Tx Header Format.
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