Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

Download PDF
ID 683193
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.3.8.1. Rx Header and Rx Data Format

Table 21.  Rx Header Field Definitions
Field Description
mdata

Metadata: User defined request ID, returned unmodified from memory request to response header.

For multi-CL memory response, the same mdata is returned for each CL.

vc_used

Virtual channel used: when using VA, this field identifies the virtual channel selected for the request by FIU. For other VCs it returns the request VC.

format

When using multi-CL memory write requests, FIU may return a single response for the entire payload or a response per CL in the payload.

  • 1’b0: Unpacked write response – Returns a response per CL. Look up the cl_num field to identify the cache line.
  • 1’b1: Packed write response – Returns a single response for the entire payload. The cl_num field gives the payload size that is: 1 CL, 2 CLs, or 4 CLs.
    Note: Write responses from the Memory Properties Factory (MPF) Intel® FPGA Basic Building Blocks is always packed when sent to the AFU
cl_num Format=0:

For a response with >1 CL data payload, this field identifies the cl_num.

2’h0 – First CL. Lowest Address

2’h1 – Second CL

2'h2 – Third CL

2’h3 – Fourth CL. Highest Address

Note: Responses may be returned out of order.
Format=1:

This field identifies the data payload size.

2’h0 – 1 CL or 64 bytes

2’h1 – 2 CL or 128 bytes

2’h3 – 4 CL or 256 bytes

hit_miss

Cache Hit/Miss status. AFU can use this to generate fine grained hit/miss statistics for various modules.

1’b0 – Cache Miss

1’b1 – Cache Hit

MMIO Length

Length for MMIO requests:

2’h0 – 4 bytes

2’h1 – 8 bytes

2'h2 - 64 bytes (for MMIO Writes only)

MMIO Address Double word (DWORD) aligned MMIO address offset, that is, byte address>>2.
UMsg ID Identifies the CL corresponding to the UMsg
UMsg Type

Two type of UMsg are supported:

1’b1 – UMsgH (Hint) without data

1’b0 – UMsg with Data
Table 22.   AFU Rx Response Encodings and Channels Mapping
Request Type Encoding Data Payload Hdr Format
t_if_ccip_c0_Rx: enum t_ccip_c0_rsp
eRSP_RDLINE 4’h0 Yes

Memory Response Header. Refer to Table 23.

Qualified with c0.rspValid
MMIO Read NA No MMIO Request Header. Refer to Table 24
MMIO Write NA Yes NA
eRSP_UMSG 4’h4 Yes/No

UMsg Response Header. Refer to Table 26. Qualified with c0.rspValid

t_if_ccip_c1_Rx: enum t_ccip_c1_rsp
eRSP_WRLINE 4’h0 No

Memory Response Header. Refer to Table 25.

Qualified with c1.rspValid
eRSP_WRFENCE 4'h4 No Wr Fence Response Header. Refer to Table 27.
eRSP_INTR 4'h6 No Interrupt Response Header. Refer to Table 28
Table 23.  C0 Memory Read Response Header Format Structure: t_ccip_c0_RspMemHdr
Bit Number of Bits Field
[27:26] 2 vc_used
[25] 1 RSVD
[24] 1 hit_miss
[23:22] 2 RSVD
[21:20] 2 cl_num
[19:16] 4 resp_type
[15:0] 16 mdata
Table 24.  MMIO Request Header Format
Bit Number of Bits Field
[27:12] 16 address
[11:10] 2 length
[9] 1 RSVD
[8:0] 9 TID
Table 25.  C1 Memory Write Response Header Format Structure: t_ccip_c1_RspMemHdr
Bit Number of Bits Field
[27:26] 2 vc_used
[25] 1 RSVD
[24] 1 hit_miss
[23] 1 format
[22] 1 RSVD
[21:20] 2 cl_num
[19:16] 4 resp_type
[15:0] 16 mdata
Table 26.  UMsg Header Format (Integrated FPGA Platform only)
Bit Number of Bits Field
[27:20] 8 RSVD
[19:16] 4 resp_type
[15] 1 UMsg Type
[14:3] 12 RSVD
[2:0] 3 UMsg ID
Table 27.  WrFence Header Format Structure: t_ccip_c1_RspFenceHdr
Bit Number of Bits Field
[27:20] 8 RSVD
[19:16] 4 resp_type
[15:0] 16 mdata
Table 28.  Interrupt Header Format Structure: t_ccip_c1_RspIntrHdr ( Intel® FPGA PAC only)
Bit Number of Bits Field
[27:26] 2 vc_used
[25:20] 6 RSVD
[19:16] 4 resp_type
[15:2] 14 RSVD
[1:0] 2 id
Level Two Title