Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

ID 683193
Date 11/04/2019
Document Table of Contents

1.3.3. Interrupts

Interrupts are not supported in the Integrated FPGA Platform.

The AFU sends an interrupt over Tx channel C1, using an interrupt ID, and receives the response over Rx channel C1.

An AFU should only have one interrupt ID issued at any given time. If the AFU does not wait for the response to return for the interrupt ID issued and issues another interrupt with the same ID, the host may not observe the arrival of the second interrupt. It is recommended for an interrupt request be serviced by software before the AFU issues an interrupt using the same interrupt ID.

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