Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

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Date 11/04/2019
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Document Table of Contents
Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.3.6. CCI-P Tx Signals

Figure 9. Tx Interface Structure Inside ccip_if_pkg.sv

There are three Tx channels:

The C0 and C1 Tx channels are used for memory requests. Both C0 and C1 Tx channels have independent flow control. The C0 Tx channel is used for memory read requests; the C1 Tx channel is used for memory write requests.

The C2 Tx channel is used to return MMIO Read response to the FIU. The CCI-P port guarantees to accept responses on C2; therefore, it has no flow control.

Figure 10. Tx Channel Structure Inside ccip_if_pkg.sv

Each Tx channel has a valid signal to qualify the corresponding header and data signals within the structure.

The following tables describe the signals that make up the CCI-P Tx interface.

Table 9.  Tx Channel Description for Channel 0
Signal Width (bits) Direction Description
pck_af2cp_sTx.c0.hdr 74 Output Channel 0 request header. Refer to Table 18.
pck_af2cp_sTx.c0.valid 1 Output When set to 1, it indicates channel 0 request header is valid.
pck_cp2af_sRx.c0TxAlmFull 1 Input

When set to 1, Tx Channel 0 is almost full. After this signal is set, AFU is allowed to send a maximum of 8 requests.

When set to 0, AFU can start sending requests immediately.

Table 10.  Tx Channel Description for Channel 1
Signal Width Direction Description
pck_af2cp_sTx.c1.hdr 80 Output Channel 1 request header. Refer to Table 12.
pck_af2cp_sTx.c1.data 512 Output Channel 1 data
pck_af2cp_sTx.c1.valid 1 Output When set to 1, it indicates channel 1 request header and data is valid.
pck_cp2af_sRx.c1TxAlmFull 1 Input

When set to 1, Tx Channel 1 is almost full. After this signal is set, AFU is allowed to send a maximum of 8 requests or data.

When set to 0, AFU can start sending requests immediately.

Table 11.  Tx Channel Description for Channel 2
Signal Width (bits) Direction Description
pck_af2cp_sTx.c2.hdr 9 Output Channel 2 response header. Refer to Table 12.
pck_af2cp_sTx.c2.mmioRdValid 1 Output When set to 1, indicates Channel 2 response header and data is valid.
pck_af2cp_sTx.c2.data 64 Output

Channel 2 data. MMIO Read Data that AFU returns to FIU.

For 4 bytes reads, data must be driven on bits [31:0].

For 8 bytes reads, AFU must drive one 8 bytes data response. Response cannot be split into two 4 bytes responses.

Level Two Title