External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide

ID 683162
Date 6/21/2021
Public
Document Table of Contents

3.1. Synthesis Design Example

The synthesis design example contains the major blocks shown in the figure below.
  • A traffic generator, which is a synthesizable Avalon® -MM example driver that implements a pseudo-random pattern of reads and writes to a parameterized number of addresses. The traffic generator also monitors the data read from the memory to ensure it matches the written data and asserts a failure otherwise.
  • An instance of the memory interface, which includes:
    • A memory controller that moderates between the Avalon® -MM interface and the AFI interface.
    • The PHY, which serves as an interface between the memory controller and external memory devices to perform read and write operations.
Figure 7. Synthesis Design Example

Synthesis Example Design

Note: If one or more of the PLL Sharing Mode, DLL Sharing Mode, or OCT Sharing Mode parameters are set to any value other than No Sharing, the synthesis design example will contain two traffic generator/memory interface instances. The two traffic generator/memory interface instances are related only by shared PLL/DLL/OCT connections as defined by the parameter settings. The traffic generator/memory interface instances demonstrate how you can make such connections in your own designs.

Did you find the information on this page useful?

Characters remaining:

Feedback Message