External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide

ID 683162
Date 6/21/2021
Document Table of Contents

3.2. Simulation Design Example

The simulation design example contains the major blocks shown in the following figure.
  • An instance of the synthesis design example. As described in the previous section, the synthesis design example contains a traffic generator, calibration component, and an instance of the memory interface. These blocks default to abstract simulation models where appropriate for rapid simulation.
  • A memory model, which acts as a generic model that adheres to the memory protocol specifications. Frequently, memory vendors provide simulation models for their specific memory components that you can download from their websites.
  • A status checker, which monitors the status signals from the external memory interface IP and the traffic generator, to signal an overall pass or fail condition.
Figure 10. Simulation Design Example

Simulation Example Design

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