External Memory Interfaces Intel® Agilex™ FPGA IP Design Example User Guide

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ID 683162
Date 6/21/2021
Public
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3. Design Example Description for External Memory Interfaces Intel® Agilex™ FPGA IP

When you parameterize and generate your EMIF IP, you can specify that the system create directories for simulation and synthesis file sets, and generate the file sets automatically.

If you select Simulation or Synthesis under Example Design Files on the Example Designs tab, the system creates a complete simulation file set or a complete synthesis file set, in accordance with your selection.

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